A novel architecture for on-chip path delay measurement

Abstract

As technology scales to 45nm and below, the deviation between predicted path delay using simulation and actual path delay on a manufactured chip increases. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive testers. In this paper, we propose a novel path delay measurement architecture called Enhanced path-based ring oscillator (Path-RO) that takes into account variations. The proposed Enhanced Path-RO can accurately and quickly measure path delay on-chip under variations with nearly no impact on functional data path. Enhanced Path-RO is perfectly suitable for fast and accurate speed binning as well by targeting speed paths on-chip even in presence of clock skew. Simulation results under variations collected by the Enhanced Path-RO inserted into ITC'99 b19 circuit demonstrate its high accuracy and efficiency.