LEAP: An accurate defect-free I/sub DDQ/ estimator

Abstract

The quiescent current (I/sub DDQ/) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ test. In this work, we present a method to estimate accurately the non-defective I/sub DDQ/ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG to obtain vectors having low/high defect-free I/sub DDQ/ currents.