Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path

Abstract

A new structure of the fast and low-area test pattern generator (TPG) composed of T-type flip-flops that can be easily integrated to the scan path is proposed in the paper. Nowadays, techniques of incorporating TPGs containing T-type flip-flops to the scan path either use asynchronous set and reset inputs of flip-flops or require adding a large amount of logic to transform TPG into the shift register. They all introduce large area overhead and degrade timing parameters of TPG. The area overhead of a new TPG structure is much less than in the case of to-day existing solutions. Moreover, it possess better timing parameters than conventionally designed TPGs. This last feature has been partially achieved due to the use of dedicated T-type flip-flop, whose design is presented in the paper. In addition, authors propose a testing method that is suitable for verifying correct functioning of both the scan-path and the new type TPGs incorporated in it.