{"title":"Simulation based Performance Analysis of a Double Gate Work Function Engineered Doped Tunnel FET","authors":"Supratim Das","doi":"10.1109/EDKCON.2018.8770435","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel work function engineered dual material gate Tunnel FET structure. The proposed device has similar structural configuration with that of a normal double gate (DG) TFET and therefore feasible in aspect of fabrication. The proposed device is run by 2D TCAD Sentaurus simulator and simulation results are analyzed. Based on simulation results, it is found that there is an improvement in drive current (1.37×102times)and subthreshold slope (~ 40 mV/decade) compared to normal DG TFET. The electrical performance of the proposed device is good by virtue of having dual material as gate electrode with different work function and composition percentage.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770435","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes a novel work function engineered dual material gate Tunnel FET structure. The proposed device has similar structural configuration with that of a normal double gate (DG) TFET and therefore feasible in aspect of fabrication. The proposed device is run by 2D TCAD Sentaurus simulator and simulation results are analyzed. Based on simulation results, it is found that there is an improvement in drive current (1.37×102times)and subthreshold slope (~ 40 mV/decade) compared to normal DG TFET. The electrical performance of the proposed device is good by virtue of having dual material as gate electrode with different work function and composition percentage.
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