Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770456
A. Chanda, J. Sengupta, C. Jacob
A series of investigation were performed on Mn films which were deposited on GaAs substrates by thermal evaporation. The Mn films exhibit a highly ordered ripple-shaped structure with good periodicity, creating an exclusive patterning tool to construct two dimensional arrays of confined microstructures. The influence of the thickness of the Mn film in producing the ripple structure was clearly observed. In addition, the annealing time was considered as the major parameter to control the ordering of the ripple structure. A model for the creation of stress-driven microstructure is also proposed which indicates that Mn thin films grow on GaAs substrates in three stages: in the primary stage, the growth occurs via two-dimensional nucleation process; as the thickness increases, the stress is released by the film via creation of additional surface roughness which produce ripples; and finally an island-like growth occurs because of the non-uniform distribution of stress along the surface of the film.
{"title":"Crystallographic Growth Pattern of Well-Ordered “ripple-Shaped” Microstructures on Mn Thin Films","authors":"A. Chanda, J. Sengupta, C. Jacob","doi":"10.1109/EDKCON.2018.8770456","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770456","url":null,"abstract":"A series of investigation were performed on Mn films which were deposited on GaAs substrates by thermal evaporation. The Mn films exhibit a highly ordered ripple-shaped structure with good periodicity, creating an exclusive patterning tool to construct two dimensional arrays of confined microstructures. The influence of the thickness of the Mn film in producing the ripple structure was clearly observed. In addition, the annealing time was considered as the major parameter to control the ordering of the ripple structure. A model for the creation of stress-driven microstructure is also proposed which indicates that Mn thin films grow on GaAs substrates in three stages: in the primary stage, the growth occurs via two-dimensional nucleation process; as the thickness increases, the stress is released by the film via creation of additional surface roughness which produce ripples; and finally an island-like growth occurs because of the non-uniform distribution of stress along the surface of the film.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124397165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770399
A. Deyasi, A. R. Chowdhury, Krishnendu Roy, A. Sarkar
Drain-to-source current of independently-driven double gate (ID-DG) MOSFET is analytically computed following Ortiz-Conde model in sub 100 nm channel length in presence of different high-K dielectrics. Fowler-Nordheim tunneling concept is invoked due to reduced dielectric thickness; and front gate control is tailored to analyze the effect on current and pinch-off voltage. Excellent agreement is observed with published literatures for high front-gate voltage when device is lightly doped; which speaks in favor of the work within dimensional constraints. Percentage change of current considering body effect is estimated for different gate bias. Result speaks in favor of low power analog applications.
{"title":"Effect of High-K Dielectric on Drain Current of ID-DG MOSFET Using Ortiz-Conde Model","authors":"A. Deyasi, A. R. Chowdhury, Krishnendu Roy, A. Sarkar","doi":"10.1109/EDKCON.2018.8770399","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770399","url":null,"abstract":"Drain-to-source current of independently-driven double gate (ID-DG) MOSFET is analytically computed following Ortiz-Conde model in sub 100 nm channel length in presence of different high-K dielectrics. Fowler-Nordheim tunneling concept is invoked due to reduced dielectric thickness; and front gate control is tailored to analyze the effect on current and pinch-off voltage. Excellent agreement is observed with published literatures for high front-gate voltage when device is lightly doped; which speaks in favor of the work within dimensional constraints. Percentage change of current considering body effect is estimated for different gate bias. Result speaks in favor of low power analog applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116949825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770446
Tara Prasanna Dash, S. Das, S. Dey, J. Jena, E. Mohapatra, C. K. Maiti
The uniaxial compressive strain has been an indispensable performance booster for p-channel FinFETs. In this work, based on extensive 3D process and device simulations, performance assessment of nanoscale tri-gate FinFETs with uniaxially strained SiGe channel (fin) has been presented. A comprehensive study based on stress tuning parameters is carried out to investigate the possible highest amount of process induced stress transfer to SiGe fin for optimization of device performance. The impact of process induced stress on carrier mobility enhancement in 7nm technology node is another major focus of this study. The stress transfer efficiency is shown for different process conditions with various Ge contents. Technology CAD simulations show that strain in the fin is large for higher Ge contents in the SiGe layer for p-channel FinFETs. For the first time, the conversion of biaxially strained SiGe to uniaxially strained SiGe via process simulation has been demonstrated, and implemented as uniaxial strained-SiGe channel (fin) in tri-gate FinFETs for high performance.
{"title":"Stress Analysis in Uniaxially Strained-SiGe Channel FinFETs at 7N Technology Node","authors":"Tara Prasanna Dash, S. Das, S. Dey, J. Jena, E. Mohapatra, C. K. Maiti","doi":"10.1109/EDKCON.2018.8770446","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770446","url":null,"abstract":"The uniaxial compressive strain has been an indispensable performance booster for p-channel FinFETs. In this work, based on extensive 3D process and device simulations, performance assessment of nanoscale tri-gate FinFETs with uniaxially strained SiGe channel (fin) has been presented. A comprehensive study based on stress tuning parameters is carried out to investigate the possible highest amount of process induced stress transfer to SiGe fin for optimization of device performance. The impact of process induced stress on carrier mobility enhancement in 7nm technology node is another major focus of this study. The stress transfer efficiency is shown for different process conditions with various Ge contents. Technology CAD simulations show that strain in the fin is large for higher Ge contents in the SiGe layer for p-channel FinFETs. For the first time, the conversion of biaxially strained SiGe to uniaxially strained SiGe via process simulation has been demonstrated, and implemented as uniaxial strained-SiGe channel (fin) in tri-gate FinFETs for high performance.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115106788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770221
S. K. Sinha, S. Tripathi, Goutam Chatterjee, Nisarga Chand
For high performance device application SGOI is a better alternative to Si substrate because of its much attractive property. TFET has been proposed as possible alternative to the conventional MOSFET. In this paper, I proposed a novel SGOI Tunnel Field Effect Transistor with VDD = 0.65 Volts, using non local BTBT model for low power VLSI applications. I studied the different aspects of mole fraction of germanium in device which finally affects the characteristics such as sub-threshold swing, Ion $mathrm{I}_{mathrm{o}mathrm{f}mathrm{f}}$ ratio. In this paper optimization at various level of the device is done in their structure, these optimization indicates the result with high $mathrm{I}_{mathrm{o}mathrm{n}}/mathrm{I}_{mathrm{o}mathrm{f}mathrm{f}}$ ratio of $3.39times 10^{9}$ and sub-threshold swing of 37 mV/ decade. In this paper Miller-capacitance and threshold-voltage is also optimized with mole fraction variation of germanium.
{"title":"Analysis of Different Characteristics of SOI-TFET with Ge Material as Source Pocket","authors":"S. K. Sinha, S. Tripathi, Goutam Chatterjee, Nisarga Chand","doi":"10.1109/EDKCON.2018.8770221","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770221","url":null,"abstract":"For high performance device application SGOI is a better alternative to Si substrate because of its much attractive property. TFET has been proposed as possible alternative to the conventional MOSFET. In this paper, I proposed a novel SGOI Tunnel Field Effect Transistor with VDD = 0.65 Volts, using non local BTBT model for low power VLSI applications. I studied the different aspects of mole fraction of germanium in device which finally affects the characteristics such as sub-threshold swing, Ion $mathrm{I}_{mathrm{o}mathrm{f}mathrm{f}}$ ratio. In this paper optimization at various level of the device is done in their structure, these optimization indicates the result with high $mathrm{I}_{mathrm{o}mathrm{n}}/mathrm{I}_{mathrm{o}mathrm{f}mathrm{f}}$ ratio of $3.39times 10^{9}$ and sub-threshold swing of 37 mV/ decade. In this paper Miller-capacitance and threshold-voltage is also optimized with mole fraction variation of germanium.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770517
Tara Prasanna Dash, S. Dey, S. Das, E. Mohaptra, J. Jena, C. K. Maiti
In nanoelectronics, the device performance evolution is limited by the down-scaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. However, it is essential to properly control the stress during process integration to understand the influence on channel transport. The aim of this work is to study the mechanical stress evolution in a tri-gate FinFET at 7nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the device. Suitability of TCAD to explore the potential of new innovative strain-engineered device structures for future generations of CMOS technology is demonstrated.
{"title":"Stress Tuning in NanoScale FinFETs at 7nm","authors":"Tara Prasanna Dash, S. Dey, S. Das, E. Mohaptra, J. Jena, C. K. Maiti","doi":"10.1109/EDKCON.2018.8770517","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770517","url":null,"abstract":"In nanoelectronics, the device performance evolution is limited by the down-scaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. However, it is essential to properly control the stress during process integration to understand the influence on channel transport. The aim of this work is to study the mechanical stress evolution in a tri-gate FinFET at 7nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the device. Suitability of TCAD to explore the potential of new innovative strain-engineered device structures for future generations of CMOS technology is demonstrated.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114165087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770404
K. Sinha, Partha Sarathi Gupta, S. Chattopadhyay, H. Rahaman
The effect of Silicon-Germanium (SiGe) volume in an embedded source and drain Si-FinFET device structure has been studied in this article. The study has been carried out thoroughly using the process and device technology computer-aided design (TCAD) simulator from Synopsys. A new technique for incorporating uniaxial tensile stress in the Silicon channel region has been introduced by fractionally SiGe embedded source/drain region in 3-dimensional FinFET architecture. It has been found that when the SiGe length in source/drain regions become equal to the length of gate region from channel-source/drain interface induce maximum tensile stress of 274 MPa in the silicon channel which improves the performance of n-type Field Effect Transistor (FET) devices. However, fully SiGe embedded source/drain region induce conventional compressive channel stress of 513 MPa which helps to increase different performance parameters of p-channel devices. Thus, for the first time, it has been reported that by controlling the stressor length/volume, both tensile and compressive strain can be introduced in the channel of a Si-FinFET device structure. The channel, source/drain, and stressor regions have been observed to control the overall nature and amount of incorporated stress and thus the proposed design is capable of improving the performance of both p-type and n-type FinFETs without any fabrication overhead.
{"title":"Incorporation of Tensile and Compressive Channel Stress by Modulating SiGe Stressor Length in Embedded Source/Drain Si-FinFET Architecture","authors":"K. Sinha, Partha Sarathi Gupta, S. Chattopadhyay, H. Rahaman","doi":"10.1109/EDKCON.2018.8770404","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770404","url":null,"abstract":"The effect of Silicon-Germanium (SiGe) volume in an embedded source and drain Si-FinFET device structure has been studied in this article. The study has been carried out thoroughly using the process and device technology computer-aided design (TCAD) simulator from Synopsys. A new technique for incorporating uniaxial tensile stress in the Silicon channel region has been introduced by fractionally SiGe embedded source/drain region in 3-dimensional FinFET architecture. It has been found that when the SiGe length in source/drain regions become equal to the length of gate region from channel-source/drain interface induce maximum tensile stress of 274 MPa in the silicon channel which improves the performance of n-type Field Effect Transistor (FET) devices. However, fully SiGe embedded source/drain region induce conventional compressive channel stress of 513 MPa which helps to increase different performance parameters of p-channel devices. Thus, for the first time, it has been reported that by controlling the stressor length/volume, both tensile and compressive strain can be introduced in the channel of a Si-FinFET device structure. The channel, source/drain, and stressor regions have been observed to control the overall nature and amount of incorporated stress and thus the proposed design is capable of improving the performance of both p-type and n-type FinFETs without any fabrication overhead.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122078891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770391
I. Mal, D. P. Samajdar, Debamita Roy
In order to investigate the effect of hydrostatic pressure and N impurities on optoelectronic properties of GaAsSbN/GaAs Quantum Well (QW), electronic band structure, band offsets, effective mass of charge carries, relative permittivity and optical gain have been calculated under the vicinity of 16 band k.p Hamiltonian. It has been anticipated that GaAsSbN/GaAs QW system would be a potential candidate for numerous optoelectronic applications such as efficient tandem solar cells, which can cover up the entire regime (850nm to 1850nm) of AM 1.5 spectra, LASER diodes for the potential applications in the 1.3−1.55 μm regime and wide range optical modulators.
{"title":"Hydrostatic Pressure Study of GaAsSbN/GaAs Quantum Well Based Optoelectronic Devices","authors":"I. Mal, D. P. Samajdar, Debamita Roy","doi":"10.1109/EDKCON.2018.8770391","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770391","url":null,"abstract":"In order to investigate the effect of hydrostatic pressure and N impurities on optoelectronic properties of GaAsSbN/GaAs Quantum Well (QW), electronic band structure, band offsets, effective mass of charge carries, relative permittivity and optical gain have been calculated under the vicinity of 16 band k.p Hamiltonian. It has been anticipated that GaAsSbN/GaAs QW system would be a potential candidate for numerous optoelectronic applications such as efficient tandem solar cells, which can cover up the entire regime (850nm to 1850nm) of AM 1.5 spectra, LASER diodes for the potential applications in the 1.3−1.55 μm regime and wide range optical modulators.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129667866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770470
Gargi Jana, M. Chanda
In this paper a simple analytical model of the drain current of the junctionless double gate junctionless MOSFET with a variable barrier height has been presented. Band non-parabolicity is also assumed to increase the efficacy of the proposed model, applicable for the ultrathin nano devices. Variable barrier height uses intra band tunneling to enhance the ION/IOFF by reducing the off current of the device significantly. Also lower sub-threshold slope can be achieved using this proposed device structure. Simulation shows that the proposed data is matched with the simulated data with high accuracy.
{"title":"Analytical Modeling of Drain Current of Junctionless Double Gate Si-MOSFET having Variable Barrier Height Considering Band Non-Parabolicity","authors":"Gargi Jana, M. Chanda","doi":"10.1109/EDKCON.2018.8770470","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770470","url":null,"abstract":"In this paper a simple analytical model of the drain current of the junctionless double gate junctionless MOSFET with a variable barrier height has been presented. Band non-parabolicity is also assumed to increase the efficacy of the proposed model, applicable for the ultrathin nano devices. Variable barrier height uses intra band tunneling to enhance the ION/IOFF by reducing the off current of the device significantly. Also lower sub-threshold slope can be achieved using this proposed device structure. Simulation shows that the proposed data is matched with the simulated data with high accuracy.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123642666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770428
S. Ghosal, P. Bhattacharyya
11This work is supported by Visvesvaraya Young Scientist Fellowship and CENSe Lab, IISc BangaloreAn integrated micro-heater based $mathrm{TiO}_{2}$ nanotube (NT) device is reported in this paper. Detailed micro-fabrication technique, structural and morphological characterization and sensing performance of the device to different alcohol vapors (e.g. Methanol, Ethanol and 2-Propanol) have been reported. The integrated Ti-Pt based micro-heater (fabricated by DC magnetron sputtering) was used to control the temperature of the sensing material $(mathrm{TiO}_{2}text{NT}]$ for the detection of different test vapors. The Temperature Coefficient of Resistance (TCR) of the sensor was determined by varying the heater temperature (27-200 °C). 500 nm oxide layer was used for the heater insulation thickness. On top of the insulated micro-heater, 100 nm of Ti thin film was sputtered. $mathrm{TiO}_{2}$ nanotubes were prepared by electrochemical anodization method. After detailed characterization, the sensor showed $sim 23.79%, sim 31.02%, sim 49.97%, sim 71.32% text{and} sim 80.39%$ response magnitude in the range of 10–400 ppm of Methanol concentration, at optimized temperature 130 °C. Selectivity study revealed relatively better Methanol sensing performance, compared to that of Ethanol and 2-Propanol.
{"title":"An Efficient Microsensor System for Selective Detection of Methanol Using TiO2 Nanotubes","authors":"S. Ghosal, P. Bhattacharyya","doi":"10.1109/EDKCON.2018.8770428","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770428","url":null,"abstract":"11This work is supported by Visvesvaraya Young Scientist Fellowship and CENSe Lab, IISc BangaloreAn integrated micro-heater based $mathrm{TiO}_{2}$ nanotube (NT) device is reported in this paper. Detailed micro-fabrication technique, structural and morphological characterization and sensing performance of the device to different alcohol vapors (e.g. Methanol, Ethanol and 2-Propanol) have been reported. The integrated Ti-Pt based micro-heater (fabricated by DC magnetron sputtering) was used to control the temperature of the sensing material $(mathrm{TiO}_{2}text{NT}]$ for the detection of different test vapors. The Temperature Coefficient of Resistance (TCR) of the sensor was determined by varying the heater temperature (27-200 °C). 500 nm oxide layer was used for the heater insulation thickness. On top of the insulated micro-heater, 100 nm of Ti thin film was sputtered. $mathrm{TiO}_{2}$ nanotubes were prepared by electrochemical anodization method. After detailed characterization, the sensor showed $sim 23.79%, sim 31.02%, sim 49.97%, sim 71.32% text{and} sim 80.39%$ response magnitude in the range of 10–400 ppm of Methanol concentration, at optimized temperature 130 °C. Selectivity study revealed relatively better Methanol sensing performance, compared to that of Ethanol and 2-Propanol.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"227 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120882097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770466
N. Paul, S. Singh
Recent improvements in the understanding and fabrication of GaN have led to its application in high frequency communication and high voltage switching systems. Requirement for operation at even higher frequency and voltages is driving the research currently on design of GaN based devices. In this paper, we present the result of our study of two-dimensional (2-D) High Electron Mobility Transistors (HEMTs) based on GaN/AlGaN/GaN heterostructure using Sentaurus TCAD tools. Exhaustive RF simulations were performed to study the effect of various device parameters such as Gate length, Gate-to-Source spacing, Gate-to-Drain spacing, etc. as well as the effect of various Gate shapes such as T-Gate, Y-Gate, etc., on the high frequency performance of the Transistor. Simulation result shows very promising result with fT and fMAX value of 1691.43 GHz and 2650.84 GHz respectively.
{"title":"Dependency of fT and fMAX on Various Device Parameters of AIGaN/GaN HEMT","authors":"N. Paul, S. Singh","doi":"10.1109/EDKCON.2018.8770466","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770466","url":null,"abstract":"Recent improvements in the understanding and fabrication of GaN have led to its application in high frequency communication and high voltage switching systems. Requirement for operation at even higher frequency and voltages is driving the research currently on design of GaN based devices. In this paper, we present the result of our study of two-dimensional (2-D) High Electron Mobility Transistors (HEMTs) based on GaN/AlGaN/GaN heterostructure using Sentaurus TCAD tools. Exhaustive RF simulations were performed to study the effect of various device parameters such as Gate length, Gate-to-Source spacing, Gate-to-Drain spacing, etc. as well as the effect of various Gate shapes such as T-Gate, Y-Gate, etc., on the high frequency performance of the Transistor. Simulation result shows very promising result with fT and fMAX value of 1691.43 GHz and 2650.84 GHz respectively.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"17 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125715129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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