Junction to case thermal resistance variability due to temperature induced package warpage

Abstract

In-situ junction-to-case thermal resistance (Theta JC) measurements are sensitive to a number of test condition factors. In this paper, the effect of electronic package die temperature on junction-to-case thermal measurements is reported over a nominal use condition temperature range of 40 to 105°C. Multiple parts were tested under a variety of boundary conditions to assess the impact of die temperature, total power dissipation, ambient cooling, and thermal parasitic heat loss through the test motherboard. The spatially resolved Thermal Interface Material I (TIM I) bond line thickness (BLT) was also quantified over a typical reflow temperature profile. These results combined with analytical and numerical modeling demonstrate that temperature induced package warpage can dramatically impact measured Theta JC values (up to 20%) due primarily to the impact on the spatially resolved TIM I bond line thickness. Such considerations should be considered by practitioners reporting Theta JC measurements. The results confirm the value of in-situ testing where package warpage is process and form factor dependent and cannot be predicted with bulk material testing data alone.