High performance computing (HPC) 3 dimensional integrated (3DI) thermal test vehicle validation effort

S. Polzer, W. Wilkins, J. Prairie, B. Gilbert, C. Haider
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Abstract

As system performance requirements for high performance computing (HPC) systems become more demanding, the need to increase component packaging density to shorten interconnect distances becomes more stringent. One technique for accomplishing this requirement is to implement 3-dimensional heterogeneous integration of system components. In an earlier publication, we described the design of a processor-memory module for a high performance computing (HPC) application space using a 3D integration (3DI) approach [1]. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30 Gb/second SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. Using thermal test chips (TTC), we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The technologies selected—semi-rigid flex, power connectors, land grid array (LGA) attachment with an anisotropic film, and cold plate-based cooling—are all commercially available, which were adapted for the test module. We were able to fabricate and conduct thermal testing of this design. This paper includes an overview of our HPC 3DI thermal test vehicle (3DI TTV) design, and compares test results between measured and simulated temperatures for the TTCs used to emulate both the memory and the processor. Unexpected differences were observed between the measured and simulated results at a corner location on the TTC. After ruling out device and test equipment issues, we discovered a silicon defect that, although it could not be modeled using our standard computational fluid dynamics (CFD) methods, appeared to explain the measured results. A rudimentary finite element analysis (FEA) analysis agreed more closely with the measured results, indicating the need for awareness of possible limitations with assumptions used in our CFD analysis.
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高性能计算(HPC)三维集成(3DI)热测试车辆验证工作
随着高性能计算(HPC)系统对系统性能的要求越来越高,增加组件封装密度以缩短互连距离的需求变得更加迫切。实现这一需求的一种技术是实现系统组件的三维异构集成。在较早的一篇文章中,我们描述了使用3D集成(3DI)方法为高性能计算(HPC)应用空间设计的处理器-内存模块[1]。该设计基于处理器-存储器模块的互连和功率传输要求,该模块能够支持64个30gb /秒的全双工SerDes, 800个处理器到存储器引脚的路由,集成的多层功率传输网络,以及能够消耗100 W/cm2标称处理器热通量的热管理解决方案。利用热测试芯片(TTC),我们设计并组装了一个带有集成电源传输网络的3D处理器-存储器模块,以研究HPC环境下3D集成封装的互连密度、集成、可测试性和返工问题。所选择的技术——半刚性柔性、电源连接器、带有各向异性薄膜的陆地电网阵列(LGA)附件和基于冷板的冷却——都是市售的,适用于测试模块。我们能够制造并进行这种设计的热测试。本文概述了我们的HPC 3DI热测试车(3DI TTV)设计,并比较了用于模拟内存和处理器的ttc的测量和模拟温度的测试结果。在TTC的一个角落位置,测量结果和模拟结果之间观察到意想不到的差异。在排除了设备和测试设备的问题后,我们发现了一个硅缺陷,尽管它无法使用我们的标准计算流体动力学(CFD)方法进行建模,但似乎可以解释测量结果。初步的有限元分析(FEA)分析与测量结果更接近,表明需要意识到CFD分析中使用的假设可能存在的局限性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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