Efficient VLSI design of CAVLC decoder of H.264 for HD videos

Abstract

The widely used H.264 video coding standard has adopted Context-based Adaptive Variable Length Coding (CAVLC) as one of its techniques for entropy encoding. In this work, VLSI design for implementing CAVLC decoder has been proposed. The design considers the speed requirements for transmission of HD videos. The architecture efficiently mixes both tree-based method and bit-parallel variable length decoding (VLD) which enhances the speed without compromising the area. The design is able to process HD frames (1080p format) at a frame rate of 30fps while working at 131 MHz clock frequency. Efficient utilization of area has been taken care off. The implemented architecture can be integrated with other blocks of H.264 to form a complete video codec.