Heng Wu, S. Seo, C. Niu, W. Wang, G. Tsutsui, O. Gluschenkov, Zuoguang Liu, A. Petrescu, A. Carr, Samuel S. Choi, S. Tsai, Chanro Park, I. Seshadri, Anuja Desilva, A. Arceo, George Yang, M. Sankarapandian, C. Prindle, K. Akarvardar, C. Durfee, Jie Yang, P. Adusumilli, Bruce Miao, J. Strane, W. Kleemeier, M. Raymond, K. Choi, F. Lie, T. Yamashita, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare
{"title":"Integrated dual SPE processes with low contact resistivity for future CMOS technologies","authors":"Heng Wu, S. Seo, C. Niu, W. Wang, G. Tsutsui, O. Gluschenkov, Zuoguang Liu, A. Petrescu, A. Carr, Samuel S. Choi, S. Tsai, Chanro Park, I. Seshadri, Anuja Desilva, A. Arceo, George Yang, M. Sankarapandian, C. Prindle, K. Akarvardar, C. Durfee, Jie Yang, P. Adusumilli, Bruce Miao, J. Strane, W. Kleemeier, M. Raymond, K. Choi, F. Lie, T. Yamashita, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare","doi":"10.1109/IEDM.2017.8268440","DOIUrl":null,"url":null,"abstract":"In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10−9 Q-cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268440","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10−9 Q-cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.
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