{"title":"The radix-2/sup k/ Viterbi decoding with transpose path metric processor","authors":"Wen-Ta Lee, Thou-Ho Chen, Liang-Gee Chen","doi":"10.1109/APCCAS.1994.514548","DOIUrl":null,"url":null,"abstract":"In this paper, we present a radix-2/sup k/ Viterbi decoding with Transpose Path Metric (TPM) processor. The TPM processor can provide a permutation function for state rearrangement with simple local interconnection. For interconnection realization, the routing complexity is less than that of the delay-commutator reported previously. In addition, a higher memory length Viterbi processor can be constructed with lower radix-2/sup k/ modules. With features of modulation and cell regularity, the radix-2/sup k/ Viterbi decoding with TPM processor is very suitable for VLSI implementation.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"153 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.1994.514548","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we present a radix-2/sup k/ Viterbi decoding with Transpose Path Metric (TPM) processor. The TPM processor can provide a permutation function for state rearrangement with simple local interconnection. For interconnection realization, the routing complexity is less than that of the delay-commutator reported previously. In addition, a higher memory length Viterbi processor can be constructed with lower radix-2/sup k/ modules. With features of modulation and cell regularity, the radix-2/sup k/ Viterbi decoding with TPM processor is very suitable for VLSI implementation.
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