Study of substrate noise and techniques for minimization

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221201

M. Peng

引用次数: 31

Abstract

This paper presents a study of substrate noise effects on analog circuits and a technique for minimizing substrate noise. Measured data of a 0.25 /spl mu/m CMOS test chip reveals that substrate noise couples through circuit asymmetries and nonlinearity, degrading analog circuit performance. An active substrate noise shaping circuit implemented on the same test chip demonstrates over 10 dB improvement in SNDR in the 0-20 kHz band of a delta-sigma modulator for substrate noise generated by an inverter array.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

研究衬底噪声和最小化技术

本文研究了衬底噪声对模拟电路的影响，并提出了一种减小衬底噪声的技术。0.25 /spl μ l /m CMOS测试芯片的测量数据表明，衬底噪声通过电路的不对称和非线性耦合，降低了模拟电路的性能。在同一测试芯片上实现的有源衬底噪声整形电路表明，对于由逆变器阵列产生的衬底噪声，δ - σ调制器在0-20 kHz频段的SNDR提高了10 dB以上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

自引率

0.00%

发文量

期刊最新文献

RF CMOS comes of age A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology On-die droop detector for analog sensing of power supply noise A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering