Siddharth Rao, K. Cai, G. Talmelli, Nathali Franchina-Vergel, Ward Janssens, H. Hody, F. Yasin, K. Wostyn, S. Couet
{"title":"Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications","authors":"Siddharth Rao, K. Cai, G. Talmelli, Nathali Franchina-Vergel, Ward Janssens, H. Hody, F. Yasin, K. Wostyn, S. Couet","doi":"10.1109/IMW56887.2023.10145991","DOIUrl":null,"url":null,"abstract":"Spin-orbit torque (SOT) magnetic random-access memory (MRAM) is a 3-terminal non-volatile memory technology promising high speed up to multi-GHz, high endurance and non-volatility. Here we show how SOT-MRAM stack can be optimized to reach performance towards an embedded last level cache memory replacing SRAM. Moreover, we show how the stack and device geometry can be optimized to increase density and how the stack properties can be optimized to perform analog in-memory computing (AiMC) functions using high resistance devices.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW56887.2023.10145991","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Spin-orbit torque (SOT) magnetic random-access memory (MRAM) is a 3-terminal non-volatile memory technology promising high speed up to multi-GHz, high endurance and non-volatility. Here we show how SOT-MRAM stack can be optimized to reach performance towards an embedded last level cache memory replacing SRAM. Moreover, we show how the stack and device geometry can be optimized to increase density and how the stack properties can be optimized to perform analog in-memory computing (AiMC) functions using high resistance devices.