Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145938
A. Bicksler, C. Miccoli, Srinath Venkatesan
A new memory device behavior has been experimentally identified and investigated in 3D NAND devices. The experimental results show that the memory device characteristics pertaining to channel properties are degraded through hightemperature stress and can be subsequentially annealed depending upon the Vt level of the cell. This newly identified NAND memory cell metastability issue is characterized and the mechanism is identified as an increase in polysilicon trap density from alternate bonding configurations within the channel film/interfaces post hydrogen passivation.
{"title":"Physical Model and Characteristics of 3D NAND Memory Cell Metastability Issues under High Temperature Stress","authors":"A. Bicksler, C. Miccoli, Srinath Venkatesan","doi":"10.1109/IMW56887.2023.10145938","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145938","url":null,"abstract":"A new memory device behavior has been experimentally identified and investigated in 3D NAND devices. The experimental results show that the memory device characteristics pertaining to channel properties are degraded through hightemperature stress and can be subsequentially annealed depending upon the Vt level of the cell. This newly identified NAND memory cell metastability issue is characterized and the mechanism is identified as an increase in polysilicon trap density from alternate bonding configurations within the channel film/interfaces post hydrogen passivation.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122740464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145825
S. Shim, J. Jang, J. Song
NAND flash memory industry has made significant progress in the density and technology since the introduction of 3D NAND flash memory. It took only a few years to change the mainstream of the NAND flash memory from 2D NAND to 3D NAND thanks to its superior cell characteristics with bit cost scalability in spite of the difficulties in process. Up to now, 3D NAND technology also has been advancing rapidly, driving bit growth scaling with the increase in the number of vertical word lines. However, NAND flash memory industry is constantly encountering the new challenges in terms of the capacity and performance. In this paper, we review trends and key technologies during the evolution of 3D NAND flash memory and the challenges NAND industry need to solve to meet the growing market requirement.
{"title":"Trends and Future Challenges of 3D NAND Flash Memory","authors":"S. Shim, J. Jang, J. Song","doi":"10.1109/IMW56887.2023.10145825","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145825","url":null,"abstract":"NAND flash memory industry has made significant progress in the density and technology since the introduction of 3D NAND flash memory. It took only a few years to change the mainstream of the NAND flash memory from 2D NAND to 3D NAND thanks to its superior cell characteristics with bit cost scalability in spite of the difficulties in process. Up to now, 3D NAND technology also has been advancing rapidly, driving bit growth scaling with the increase in the number of vertical word lines. However, NAND flash memory industry is constantly encountering the new challenges in terms of the capacity and performance. In this paper, we review trends and key technologies during the evolution of 3D NAND flash memory and the challenges NAND industry need to solve to meet the growing market requirement.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124820995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145940
F. Müller, S. De, M. Lederer, R. Hoffmann, R. Olivo, T. Kämpfe, K. Seidel, T. Ali, H. Mulaosmanovic, Stefan Dünkel, J. Müller, S. Beyer, G. Gerlach
We report on the multi-level-cell (MLC) operation of AND-connected ferroelectric FET (FeFET) arrays and their suitability for Compute-in-Memory (CiM) applications. The switching behavior and device variation of FeFETs in a passive AND array test-structure configuration is investigated. From this, we derive suitable write schemes and inhibit schemes capable of protecting any FeFET state. This enables the MLC operation of the AND arrays, yielding a performance suitable for CiM applications. We investigate the impact of the obtained bit-error-rate (BER) of 4% in inference-only operation, which shows only a 1% degradation from the floating-point (FP) accuracy for CIFAR-10 datasets with LeNET.
{"title":"Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications","authors":"F. Müller, S. De, M. Lederer, R. Hoffmann, R. Olivo, T. Kämpfe, K. Seidel, T. Ali, H. Mulaosmanovic, Stefan Dünkel, J. Müller, S. Beyer, G. Gerlach","doi":"10.1109/IMW56887.2023.10145940","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145940","url":null,"abstract":"We report on the multi-level-cell (MLC) operation of AND-connected ferroelectric FET (FeFET) arrays and their suitability for Compute-in-Memory (CiM) applications. The switching behavior and device variation of FeFETs in a passive AND array test-structure configuration is investigated. From this, we derive suitable write schemes and inhibit schemes capable of protecting any FeFET state. This enables the MLC operation of the AND arrays, yielding a performance suitable for CiM applications. We investigate the impact of the obtained bit-error-rate (BER) of 4% in inference-only operation, which shows only a 1% degradation from the floating-point (FP) accuracy for CIFAR-10 datasets with LeNET.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132132561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145963
Suhwan Lim, Samki Kim, Changhee Lee, Hyeongwon Choi, Nambin Kim, Jaehun Jung, Hanvit Yang, Taehyeok Kim, Junhee Lim, Daewon Ha, Sunghoi Hur, J. Jang, Y. Shin, J. Song
We propose a novel structure to enhance transverse band-to-band tunneling (T-BTBT) for the erase scheme assisted by gate induced drain leakage (GIDL) to improve the erase speed of high density vertical NAND (VNAND). In order to increase the GIDL current, we adopt the structure, in which the bit-line PAD (BL PAD) is surrounded by the GIDL transistors, to the top part of the VNAND memory string. In this structure, the $n^{+}-$doped region called the BL PAD is pulled down so that its bottom is placed below the bottom of the first GIDL transistor and the gate-to-drain overlap area is increased. Furthermore, the $n^{+}-$doped poly-Si region of the BL PAD is covered with the undoped poly-Si layer to reduce the n type doping concentration in the overlap region between the BL PAD and GIDL transistor. Thus, the depletion region is formed between the $n^{+}-$doped BL PAD and undoped channel poly-Si regions. Then, in contrast to the conventional structure where the longitudinal BTBT (L-BTBT) current dominates, the TBTBT current occurs in such a depletion region and becomes the dominant GIDL current. The proposed structure on a VNAND device array is experimentally verified, and we obtain the GIDL current which is 5 times larger than that in VNAND to which the conventional ion implantation structure applied. Such a large GIDL current is suitable even for VNAND with more than 1000 layers of word line stacked.
{"title":"Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND","authors":"Suhwan Lim, Samki Kim, Changhee Lee, Hyeongwon Choi, Nambin Kim, Jaehun Jung, Hanvit Yang, Taehyeok Kim, Junhee Lim, Daewon Ha, Sunghoi Hur, J. Jang, Y. Shin, J. Song","doi":"10.1109/IMW56887.2023.10145963","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145963","url":null,"abstract":"We propose a novel structure to enhance transverse band-to-band tunneling (T-BTBT) for the erase scheme assisted by gate induced drain leakage (GIDL) to improve the erase speed of high density vertical NAND (VNAND). In order to increase the GIDL current, we adopt the structure, in which the bit-line PAD (BL PAD) is surrounded by the GIDL transistors, to the top part of the VNAND memory string. In this structure, the $n^{+}-$doped region called the BL PAD is pulled down so that its bottom is placed below the bottom of the first GIDL transistor and the gate-to-drain overlap area is increased. Furthermore, the $n^{+}-$doped poly-Si region of the BL PAD is covered with the undoped poly-Si layer to reduce the n type doping concentration in the overlap region between the BL PAD and GIDL transistor. Thus, the depletion region is formed between the $n^{+}-$doped BL PAD and undoped channel poly-Si regions. Then, in contrast to the conventional structure where the longitudinal BTBT (L-BTBT) current dominates, the TBTBT current occurs in such a depletion region and becomes the dominant GIDL current. The proposed structure on a VNAND device array is experimentally verified, and we obtain the GIDL current which is 5 times larger than that in VNAND to which the conventional ion implantation structure applied. Such a large GIDL current is suitable even for VNAND with more than 1000 layers of word line stacked.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145961
Sola Woo, Gihun Choe, A. Khan, S. Datta, Shimeng Yu
Ferroelectric-metal field-effect transistor (FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for multi-level cell (MLC) operation. The FeMFET with a gate-stack of metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) is used for improving memory window to $1.60mathrm{~V}$ and alleviating variability caused by ferroelectric phase variation for MLC operation. In addition, the read-out current is examined by increasing the vertical gate-stack from 256-layer to 512-layer using page buffer circuit for sensing operation. Leveraging TCAD modeling and SPICE simulation, we demonstrate that FeMFET-based 3D NAND can operate 512-layer with sufficient sense margin for MLC operation.
{"title":"Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash","authors":"Sola Woo, Gihun Choe, A. Khan, S. Datta, Shimeng Yu","doi":"10.1109/IMW56887.2023.10145961","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145961","url":null,"abstract":"Ferroelectric-metal field-effect transistor (FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for multi-level cell (MLC) operation. The FeMFET with a gate-stack of metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) is used for improving memory window to $1.60mathrm{~V}$ and alleviating variability caused by ferroelectric phase variation for MLC operation. In addition, the read-out current is examined by increasing the vertical gate-stack from 256-layer to 512-layer using page buffer circuit for sensing operation. Leveraging TCAD modeling and SPICE simulation, we demonstrate that FeMFET-based 3D NAND can operate 512-layer with sufficient sense margin for MLC operation.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125044434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145932
Y. Tkachev, S. Lemke, L. Schneider, G. Festes, P. Ghazavi
The process of ESF3 memory cell analog tuning for neuromorphic applications was studied with a single-electron accuracy. It was experimentally shown that the number of electrons injected to the floating gate during incremental programming pulses follows Poisson distribution, which sets a fundamental limit for the minimum width of the tuned cell current/threshold voltage distributions. The new method for analog tuning, based on capacitive coupling, allows one to override the electron charge granularity limitation, and to achieve the sub-elementary charge tuning accuracy.
{"title":"Analog Tuning of Floating-Gate Cells with Sub-Elementary Charge Accuracy for In-Memory Computing Applications","authors":"Y. Tkachev, S. Lemke, L. Schneider, G. Festes, P. Ghazavi","doi":"10.1109/IMW56887.2023.10145932","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145932","url":null,"abstract":"The process of ESF3 memory cell analog tuning for neuromorphic applications was studied with a single-electron accuracy. It was experimentally shown that the number of electrons injected to the floating gate during incremental programming pulses follows Poisson distribution, which sets a fundamental limit for the minimum width of the tuned cell current/threshold voltage distributions. The new method for analog tuning, based on capacitive coupling, allows one to override the electron charge granularity limitation, and to achieve the sub-elementary charge tuning accuracy.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129411633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145821
Astha Khandelwal, R. Chopdekar, Akash Surampalli, K. Tiwari, Naveen Negi, A. Kalitsov, L. Wan, J. Katine, Derek Stewart, T. Santos, Yen-Lin Huang, R. Ramesh, B. Prasad
Conventional spintronics-based memory devices use an electrical current in elegant ways to control the direction and dynamics of electrons’ spin, yet at higher energy cost and lower device endurance. Therefore, keeping pace with the growing demand for faster, smaller, and ultra-low-power electronic devices, research in the field of voltage control of magnetism has intensified recently with the promises to deliver ultra-low-power operating non-volatile memory solutions for next-generation computing systems. Here, we present our recent efforts in voltage-controlled magnetism via different approaches; voltage-controlled magnetic anisotropy (VCMA), voltage-controlled exchange coupling (VCEC), and multiferroic-based magnetoelectric coupling (MEC) for spintronics applications. These studies yielded several new findings. Large tunability of perpendicular magnetic anisotropy (PMA) has been achieved with the insertion of the Pt layer at the MgO/Ferromagnet interface. The modulation of the interlayer exchange coupling with the Ru spacer layer has been demonstrated by using non-ionic liquid gating such as MgO. Besides this, we have also shown the modulation of the magnetism by utilizing the magneto-electric coupling effect in a bismuth ferrite-based multiferroic system. These efforts provide several routes to modulate the resistance states of spintronic devices at low power and bring forth a vast playground to develop next-generation energy-efficient computing devices.
{"title":"Voltage Control of Magnetism: Low-Power Spintronics","authors":"Astha Khandelwal, R. Chopdekar, Akash Surampalli, K. Tiwari, Naveen Negi, A. Kalitsov, L. Wan, J. Katine, Derek Stewart, T. Santos, Yen-Lin Huang, R. Ramesh, B. Prasad","doi":"10.1109/IMW56887.2023.10145821","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145821","url":null,"abstract":"Conventional spintronics-based memory devices use an electrical current in elegant ways to control the direction and dynamics of electrons’ spin, yet at higher energy cost and lower device endurance. Therefore, keeping pace with the growing demand for faster, smaller, and ultra-low-power electronic devices, research in the field of voltage control of magnetism has intensified recently with the promises to deliver ultra-low-power operating non-volatile memory solutions for next-generation computing systems. Here, we present our recent efforts in voltage-controlled magnetism via different approaches; voltage-controlled magnetic anisotropy (VCMA), voltage-controlled exchange coupling (VCEC), and multiferroic-based magnetoelectric coupling (MEC) for spintronics applications. These studies yielded several new findings. Large tunability of perpendicular magnetic anisotropy (PMA) has been achieved with the insertion of the Pt layer at the MgO/Ferromagnet interface. The modulation of the interlayer exchange coupling with the Ru spacer layer has been demonstrated by using non-ionic liquid gating such as MgO. Besides this, we have also shown the modulation of the magnetism by utilizing the magneto-electric coupling effect in a bismuth ferrite-based multiferroic system. These efforts provide several routes to modulate the resistance states of spintronic devices at low power and bring forth a vast playground to develop next-generation energy-efficient computing devices.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124572286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We introduce a cost-effective, reliable and energy-efficient embedded-flash memory IP for IoT, industry, and automotive. A Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)type memory is embedded on 130BCD+ process platform with only three additional mask steps. Performance including qualification has been checked as expected at TSMC. By applying trapdepth-controlled SiN film to the SONOS memory, data storage more than 10 years at 200oC is achieved.
{"title":"SONOS Embedded Flash IP Using Trap-Depth-Controlled SiN Film Enabling Data Retention more than 10 years at 200°C","authors":"Y. Taniguchi, Shoji Yoshida, Teruhiko Egashira, ChihBin Kuo, Yi-Da Shie, YuChun Wang, ChenYu Huang, Tsuyoshi Tamatsu, Keiji Okamoto, Masanobu Hishiki, Yasushi Sasaki, Fukuo Owada, Nobuhiko Ito, Y. Shinagawa, ChihMing Kuo, S. Noda, Toshikazu Matsui, Kosuke Okuyama","doi":"10.1109/IMW56887.2023.10145990","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145990","url":null,"abstract":"We introduce a cost-effective, reliable and energy-efficient embedded-flash memory IP for IoT, industry, and automotive. A Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)type memory is embedded on 130BCD+ process platform with only three additional mask steps. Performance including qualification has been checked as expected at TSMC. By applying trapdepth-controlled SiN film to the SONOS memory, data storage more than 10 years at 200oC is achieved.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121358176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145966
Xianzhou Shao, Junshuai Chai, Min Liao, Jiahui Duan, Fengbin Tian, Xiaoyu Ke, Xiaoqing Sun, Hao Xu, J. Xiang, Xiaolei Wang, Wenwu Wang
The endurance degradation mechanism in Si FeFET has attracted great research interest. However, the reports mainly focused on large-scale devices, owing to the external current measurement limitations of modern equipment. In this work, we study the endurance degradation mechanism in the scaled n-FeFET by in-situ Vth measurement to overcome the size limitation. We find that excess electron injection rather than hole injection plays a key role in the charge trapping behavior. As the endurance cycles increase, the Vth after the program pulse positively shifts due to less electron de-trapping. The Vth after erase pulse negatively shifts due to more hole trapping when the Vg changes from -1V to -4V and no hole de-trapping occurs when the Vg changes from -4V to 0 V. The donor trap generation and hole trapping are the dominant factors of endurance failure in the scaled nFeFET.
{"title":"Comprehensive Study of Endurance Fatigue in the Scaled Si FeFET by in-situ Vth Measurement and Endurance Enhancement Strategy","authors":"Xianzhou Shao, Junshuai Chai, Min Liao, Jiahui Duan, Fengbin Tian, Xiaoyu Ke, Xiaoqing Sun, Hao Xu, J. Xiang, Xiaolei Wang, Wenwu Wang","doi":"10.1109/IMW56887.2023.10145966","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145966","url":null,"abstract":"The endurance degradation mechanism in Si FeFET has attracted great research interest. However, the reports mainly focused on large-scale devices, owing to the external current measurement limitations of modern equipment. In this work, we study the endurance degradation mechanism in the scaled n-FeFET by in-situ Vth measurement to overcome the size limitation. We find that excess electron injection rather than hole injection plays a key role in the charge trapping behavior. As the endurance cycles increase, the Vth after the program pulse positively shifts due to less electron de-trapping. The Vth after erase pulse negatively shifts due to more hole trapping when the Vg changes from -1V to -4V and no hole de-trapping occurs when the Vg changes from -4V to 0 V. The donor trap generation and hole trapping are the dominant factors of endurance failure in the scaled nFeFET.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127710350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145967
Song-Hyeon Kuk, Jaehoon Han, Bong-Ho Kim, Junpyo Kim, Sang-Hyeon Kim
Recently the demand for higher drain current and scalable gate stack thickness arises for next-generation 3D NAND flash, due to the physical limit of cells and stacked layers over 1,000. While the N-channel ferroelectric field-effect-transistor (n-FEFET) has been studied to overcome the limit, it brings the critical reliability issue due to parasitic electron trapping during the program and read, which degrades retention, endurance and induces disturbance and cell failure. We show the feasibility of 2-bit multi-level-cell (MLC) p-channel FEFET (p-FEFET) for (embedded) NAND flash memory application. P-FEFET intrinsically has higher on-current than n-FEFET. It is due to the absence of hole trapping, which leads to ferroelectric charge boosting at the channel. Other properties (retention, disturbance, etc) also show that p-FEFET has remarkably improved electrical characteristics when it is targeted for NAND flash, rather than nFEFET. Finally, we propose a strategy for engineering the pFENAND device.
{"title":"Proposal of P-Channel FE NAND with High Drain Current and Feasible Disturbance for Next Generation 3D NAND","authors":"Song-Hyeon Kuk, Jaehoon Han, Bong-Ho Kim, Junpyo Kim, Sang-Hyeon Kim","doi":"10.1109/IMW56887.2023.10145967","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145967","url":null,"abstract":"Recently the demand for higher drain current and scalable gate stack thickness arises for next-generation 3D NAND flash, due to the physical limit of cells and stacked layers over 1,000. While the N-channel ferroelectric field-effect-transistor (n-FEFET) has been studied to overcome the limit, it brings the critical reliability issue due to parasitic electron trapping during the program and read, which degrades retention, endurance and induces disturbance and cell failure. We show the feasibility of 2-bit multi-level-cell (MLC) p-channel FEFET (p-FEFET) for (embedded) NAND flash memory application. P-FEFET intrinsically has higher on-current than n-FEFET. It is due to the absence of hole trapping, which leads to ferroelectric charge boosting at the channel. Other properties (retention, disturbance, etc) also show that p-FEFET has remarkably improved electrical characteristics when it is targeted for NAND flash, rather than nFEFET. Finally, we propose a strategy for engineering the pFENAND device.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128176809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：