An algorithmic analog-to-digital converter

Abstract

ANALOG TO DIGITAL CONVERTERS perform digital logic, analog comparison and analog arithmetic. While digital logic and analog comparison are readily performed in LSI form, analog arithmetic has been largely excluded. For this reason, most single chip A/D converters use counting algorithms (such as dual slope) which are slow but which require only modest analog capability. .4 cyclic A/D converter’ can provide both a means of implcmenting successive approximation A/D converters and a means of performing general purpose analog arithmetic. This type of converter is ideal for realization using precision-ratioed capacitors A prototy e circuit using an analog CMOS process has been fabricated . The circuit features A/D conversion rates of 5 ps per bit, infinite resolution, 10 bits accuracy, and programmability, on a 3200 square mil die area. A simplified schematic of the A/D converter is shown in Figure 1. Two amplifiers, five ratio-matched capacitors ( 5 1 C ~ ) and two switches form a recirculating analog shift register wlth a gain of two. Three switches permit loading the register with an analog input and adding or subtracting the reference. A comparator to test the sign of output V, completes the circuit. A timing diagram showing the circuit in operation is shown in Figure 2. To start conversion the register is cleared by bringing both V1 and V2 high while the input is sampled by connecting C1 to Vin. This forces both V, and Yy to zero. During the second half of the initial cycle, C1 is connected t9 the analog ground and VI is brought low. This causes a charge of Cl*VIN to flow from C1 to C2. Since C1 and C2 are equal in value this will cause V, to be equal to the sampled value of VIN, and the comparator will indicate the sign of the sampled voltage. To determine the next bit V2 is brought low and VI is raised, while C1 is connected to ground (if the sign was positive) or to VREF (if the sign was negative). This causes the voltage Vx to be transferred to Vy, while 17, is forced to zero. At this point the charge in C1 is k CL*VREF, and the charge in Cg is C~*VIN. 2