Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155627
C. Chao, R. Bernick, R. Ying, K. Weller, D. Lee, E. Nakaji
{"title":"Pulsed IMPATT diode oscillators above 200 GHz","authors":"C. Chao, R. Bernick, R. Ying, K. Weller, D. Lee, E. Nakaji","doi":"10.1109/ISSCC.1977.1155627","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155627","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155623
K. Hareyama, K. Yoshimura, K. Murase
A HIGHLY ACCURATE A/D convcrter has been required in data handling systems for a microprocessor and in digital multimeters. Responding to this recent demand, a CMOS monolithic structure has been widely employed in combination with the dual slope technique’ 7’. The CMOS process, however, places a limitation on the resolution of an A(D converter at 3% digits. In the dual slope technique, on the other hand, a feedback loop is constructed between the analog and the digital subsystems. This arrangement degrades the electrical isolation between the two systems.
{"title":"A bipolar monolithic analog subsystem for a 4½ digit A/D converter","authors":"K. Hareyama, K. Yoshimura, K. Murase","doi":"10.1109/ISSCC.1977.1155623","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155623","url":null,"abstract":"A HIGHLY ACCURATE A/D convcrter has been required in data handling systems for a microprocessor and in digital multimeters. Responding to this recent demand, a CMOS monolithic structure has been widely employed in combination with the dual slope technique’ 7’. The CMOS process, however, places a limitation on the resolution of an A(D converter at 3% digits. In the dual slope technique, on the other hand, a feedback loop is constructed between the analog and the digital subsystems. This arrangement degrades the electrical isolation between the two systems.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122949613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155670
J. Price, S. Kelley
{"title":"A precision slope polarity switch for a monolithic telephone- quality deltamodulator","authors":"J. Price, S. Kelley","doi":"10.1109/ISSCC.1977.1155670","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155670","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121866655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155645
A. Dingwall
A MONOLITHIC PHASE-LOCKED LOOP frequency synthesizer for CB will be described. The chip, based on the high speed bulk C2L/CMOS self-aligned silicon-gate technology, is capable of synthesizing frequencies directly for the 40 CB channels in the 26.965-27.405 MHz band. Both high side injection frequencies (37.66-38.10MHz) and low side injection frequencies (16.27-16.71) for a 10.695 MHz intermediate frequency have been demonstrated with this device. Spectral purity, which depends on frequency, for synthesized frequencies is typically 75 dB a t 17 MHz and appears satisfactory for low cost CB transceivers, but is ultimately limited by cross talk on one chip. Studies which also have included an equivalent 2-chip system with the VCO in a separate package, demonstrated that 2-chips can give substantially higher spectral purity and synthesized bandwidth. The selection of a monolithic versus 2-chip system and the most favorable transceiver architecture provide an interesting set of cost versus performance and convenience tradeoffs.
{"title":"Monolithic C2L/CMOS frequency synthesizer for CB","authors":"A. Dingwall","doi":"10.1109/ISSCC.1977.1155645","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155645","url":null,"abstract":"A MONOLITHIC PHASE-LOCKED LOOP frequency synthesizer for CB will be described. The chip, based on the high speed bulk C2L/CMOS self-aligned silicon-gate technology, is capable of synthesizing frequencies directly for the 40 CB channels in the 26.965-27.405 MHz band. Both high side injection frequencies (37.66-38.10MHz) and low side injection frequencies (16.27-16.71) for a 10.695 MHz intermediate frequency have been demonstrated with this device. Spectral purity, which depends on frequency, for synthesized frequencies is typically 75 dB a t 17 MHz and appears satisfactory for low cost CB transceivers, but is ultimately limited by cross talk on one chip. Studies which also have included an equivalent 2-chip system with the VCO in a separate package, demonstrated that 2-chips can give substantially higher spectral purity and synthesized bandwidth. The selection of a monolithic versus 2-chip system and the most favorable transceiver architecture provide an interesting set of cost versus performance and convenience tradeoffs.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116305280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155685
B. Elmer, W. Tchon, A. Denboer, S. Kohyama, K. Hirabayashi, I. Nojima
technique in combination with laser burned fuses. During chip test, good and bad blocks are identified and the bad blocks are disconnected from the power supply by laser burned fuses. Each good block has its shorted address line fuse burned out which puts it in series with the othcr good blocks; Figure 2. No special masks are required. The good blocks are linked together by a serial addressing technique. In effect, thc linked blocks can be thought of as bit positions in a shift register such that if a “1” is inserted into the register, it can be shifted thru the register (blocks). Thus, to address a block, the “1” is shifted to the desired block and a common enable line is then activated. Data can then be written or read from the addressed block. Thus, at the system level, it is only necessary to guarantee a certain total number of good blocks to span the address range. No special method of block identification or bookkeeping of parts is required; this simplifies use.
{"title":"Fault tolerant 92160 bit multiphase CCD memory","authors":"B. Elmer, W. Tchon, A. Denboer, S. Kohyama, K. Hirabayashi, I. Nojima","doi":"10.1109/ISSCC.1977.1155685","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155685","url":null,"abstract":"technique in combination with laser burned fuses. During chip test, good and bad blocks are identified and the bad blocks are disconnected from the power supply by laser burned fuses. Each good block has its shorted address line fuse burned out which puts it in series with the othcr good blocks; Figure 2. No special masks are required. The good blocks are linked together by a serial addressing technique. In effect, thc linked blocks can be thought of as bit positions in a shift register such that if a “1” is inserted into the register, it can be shifted thru the register (blocks). Thus, to address a block, the “1” is shifted to the desired block and a common enable line is then activated. Data can then be written or read from the addressed block. Thus, at the system level, it is only necessary to guarantee a certain total number of good blocks to span the address range. No special method of block identification or bookkeeping of parts is required; this simplifies use.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116317817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155637
I. Young, David A. Hodges, Paul R. Gray
SINCE MOS TECHNOLOGY provides good switches and high quality capacitors, it is useful to reformulate old problems in a way that is amenable to solution by their use. The paper from 1977 shows that this concept extends even to filter synthesis. A conventional active filter depends on the time constants of RC products. This filter depends on an external reference frequency, which is well controlled (and adjustable to facilitate electronic tuning), and on capacitor matching (ratios accurate to the order of 0.1% are achieved in this paper). Several high-gain (2000), fast settling (8μs to 0.5%) operational amplifiers are demonstrated for the first time in this paper. Total integration and high performance have made the switched-capacitor filter a valuable functional block in modern communications systems.
{"title":"Analog NMOS sampled-data recursive filter","authors":"I. Young, David A. Hodges, Paul R. Gray","doi":"10.1109/ISSCC.1977.1155637","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155637","url":null,"abstract":"SINCE MOS TECHNOLOGY provides good switches and high quality capacitors, it is useful to reformulate old problems in a way that is amenable to solution by their use. The paper from 1977 shows that this concept extends even to filter synthesis. A conventional active filter depends on the time constants of RC products. This filter depends on an external reference frequency, which is well controlled (and adjustable to facilitate electronic tuning), and on capacitor matching (ratios accurate to the order of 0.1% are achieved in this paper). Several high-gain (2000), fast settling (8μs to 0.5%) operational amplifiers are demonstrated for the first time in this paper. Total integration and high performance have made the switched-capacitor filter a valuable functional block in modern communications systems.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133556079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155700
O. Petersen, C. Bradford, R. Cranmer
A WAVEGUIDE CIRCUIT (Figure 1) has been designed and constructed to measure impedance a t millimeter wave frequencies. To calculate the load impedance, known standards were used to characterize the network transformation between the p l y e of measurement and the load location. Measurements were performed at 54.2 GHz on specially fabricated loads and on mm-wave PIN diodes. A series of independent measurements were made to determine the relative phase and magnitude of the complex reflection coefficient of the load. Bolometer measurements at the output of the 3-dB coupler are essential to the circuit design. The phase was measured by the amount of cancellation which occurs when the reflected signal is fed into the 3-dB four-port directional coupler and compared to a reference signal fed into the other input port. The magnitude was measured by comparing the signal reflected from the load to that reflected by the reference short (waveguide switch #l) . During the latter measurement, the reference signal is terminated (waveguide switch #2).
{"title":"Impedance measurements at millimeter wave frequencies (54.2 GHz)","authors":"O. Petersen, C. Bradford, R. Cranmer","doi":"10.1109/ISSCC.1977.1155700","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155700","url":null,"abstract":"A WAVEGUIDE CIRCUIT (Figure 1) has been designed and constructed to measure impedance a t millimeter wave frequencies. To calculate the load impedance, known standards were used to characterize the network transformation between the p l y e of measurement and the load location. Measurements were performed at 54.2 GHz on specially fabricated loads and on mm-wave PIN diodes. A series of independent measurements were made to determine the relative phase and magnitude of the complex reflection coefficient of the load. Bolometer measurements at the output of the 3-dB coupler are essential to the circuit design. The phase was measured by the amount of cancellation which occurs when the reflected signal is fed into the 3-dB four-port directional coupler and compared to a reference signal fed into the other input port. The magnitude was measured by comparing the signal reflected from the load to that reflected by the reference short (waveguide switch #l) . During the latter measurement, the reference signal is terminated (waveguide switch #2).","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116901939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155704
C. Liechti
In our increasingly digital world, there is a need for faster and faster data processing capability. New systems requiring gigabit data rates for measurement instrumentation, digital communication and radar signal processing are presently in the planning stage. A similar trend toward wider band operation exists for analog circuits such as A/D converters, sample and hold circuits, signal and operational amplifiers.
{"title":"What lies ahead for analog and digital monolithic ICs at microwave frequencies?","authors":"C. Liechti","doi":"10.1109/ISSCC.1977.1155704","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155704","url":null,"abstract":"In our increasingly digital world, there is a need for faster and faster data processing capability. New systems requiring gigabit data rates for measurement instrumentation, digital communication and radar signal processing are presently in the planning stage. A similar trend toward wider band operation exists for analog circuits such as A/D converters, sample and hold circuits, signal and operational amplifiers.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155649
T. Frederiksen, W. Howard, D. Monticelli
RECENT ADVANCES in silicon processing have made i t possible t o design a bipolar camera control IC, including the silicon photodiode, on a single chip; previous electronic camera control systems have used multiple chips or less desirable cadmium-sulphide, CdS, cells. This IC operates without external components and provides linear control of the shutter and two-position aperture selection in addition t o a low light warning and a battery check. Each die is calibrated during wafer sort using a reference light source by a computer controlled metal link blowing technique. The chip is mounted in an 8-pin DIL package, Figure 4, which is molded in a clear compound. A small recess is formed in the package t o allow a light filter to be convenientlyinserted, thereby reducing the infrared response. A second lay-er of aluminum is used on the die t o shield the low level control circuitry from the incident light. Current was used as the analog of scene brightness because of the dynamic range and compatibility with bipolar circuitry. Special processing was developed to provide a blue-enhanced photodiode and transistors with good hFE holdup to handle the low level currents. A shallow photodlode junction was created by use of ion implantation to boost the normalized conversion efficiency to 60% in the visible light range. Low temperature processing and anneals,provide typical NPN hFE s of 100 and PNP hFE s of 50 at 1OnA collector current, while simultaneouslyholding junction leakages t o less than 1pA at room temperature. The filtered scene illumination is linearly convertcd t o current in the photodiode. The input differential amplifier, Figure 2, biases this device and replicates the photocurrent in a multiplicity of outputs. For near zero leakage a bias of 0V is needed, but a requirement that the shutter time out in total darkness necessitated a circuit which encourages the diode t o provide some limited dark current. The diodes at the noninverting input arc fixed biased whereas those in series with the photodiode carry I), (-4nA/Fc). Should I x 0, the latter diodes have n o voltage drop and the photodiode would approach a 1 V reverse bias. This stimulates leakage currcnt which increases the diode drops and tends to minimize and thereby regulate the leakage. Photodiode current, whether thermal or light induced, is provided by the upper PNPs through the action of the loop. The Ib of the NPN at the inverting input represents an error source which is reduced to less than 1% by adaptively biasing the tail current of the differential amplifier. This light dependent biasing technique improves the transient response of the loop, which is necessary .to realize proper exposure time when light is returned from a flash-illuminated subject; earlier cameras, which used the slower CdS cell, could not respond to this rqturncd light and would therefore produce an overexposed picture. Sufficient loop gain is provided t o insure linearity over the incident light range of in
硅加工的最新进展使得在单个芯片上设计双极相机控制IC(包括硅光电二极管)成为可能;以前的电子相机控制系统使用多个芯片或不太理想的硫化镉、cd、电池。该IC无需外部组件即可运行，除了低光警告和电池检查外，还提供快门和双位置光圈选择的线性控制。在晶圆分选过程中，通过计算机控制的金属链吹制技术，使用参考光源对每个模具进行校准。该芯片安装在8针DIL封装中，如图4所示，该封装采用透明化合物成型。在封装中形成一个小凹槽，以便方便地插入滤光片，从而减少红外响应。在模具上使用第二层铝来屏蔽低电平控制电路免受入射光的影响。由于动态范围和双极电路的兼容性，采用电流作为场景亮度的模拟量。开发了特殊的处理方法，以提供具有良好hFE保持率的蓝色增强光电二极管和晶体管来处理低电平电流。在可见光范围内，利用离子注入形成了一个浅光二极管结，将归一化转换效率提高到60%。低温处理和退火，在1OnA集电极电流下提供典型的NPN hFE为100和PNP hFE为50，同时在室温下保持结漏小于1pA。滤过的场景照明在光电二极管中线性转换为电流。输入差分放大器，如图2所示，使该器件偏置并在多个输出中复制光电流。对于接近零泄漏，需要0V的偏置，但是要求在完全黑暗中关闭时间需要一个电路来鼓励二极管提供一些有限的暗电流。非反相输入端的二极管是固定偏置的，而与光电二极管串联的二极管携带I)， (-4nA/Fc)。如果I x 0，后一个二极管有零电压降，光电二极管将接近1 V反向偏置。这刺激泄漏电流，增加二极管下降，并倾向于最小化，从而调节泄漏。光电二极管电流，无论是热电流还是光感应电流，都是由上部pnp通过回路的作用提供的。反相输入端的NPN的Ib表示一个误差源，通过自适应偏置差分放大器的尾电流将误差源减小到小于1%。这种与光相关的偏置技术改善了回路的瞬态响应，这对于实现从闪光灯照射的物体返回的光的适当曝光时间是必要的;早期的相机，使用较慢的cd电池，不能响应这种反向cd光，因此会产生过度曝光的照片。提供足够的环路增益以确保在入射光范围内的线性度(“300:l”)，并且环路由C光电二极管的结电容C补偿频率。光电流和各种参考电流之间的比较发生在低至2nA的水平。因此，有必要有一个参考电流发生器，它不存在复合泄漏和电流减小电路中的fe误差问题。再注入器电流划分，图3，最大限度地减少了这些误差，可以在一个外延桶中制造。链中的第一个PNP在发射极处输入一个大值，易于导出的参考电流(10pA)。围绕该发射极的集电极缩放提供了初始10:1的电流减小。较小的集电极连接到后续装置的发射极，并且两个区域都保持不带电。为了保持电荷中性，必须将收集到的电流重新注入。电流再注入由小集电极和下一个发射极根据相对面积共享。下一个PNP结构的行为就像公共基第一个设备。三级联提供电流划分为5000:1，并且可以获得有用的中间输出，而不是将剩余电流分流到地。
{"title":"A single-chip, all bipolar, camera control IC","authors":"T. Frederiksen, W. Howard, D. Monticelli","doi":"10.1109/ISSCC.1977.1155649","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155649","url":null,"abstract":"RECENT ADVANCES in silicon processing have made i t possible t o design a bipolar camera control IC, including the silicon photodiode, on a single chip; previous electronic camera control systems have used multiple chips or less desirable cadmium-sulphide, CdS, cells. This IC operates without external components and provides linear control of the shutter and two-position aperture selection in addition t o a low light warning and a battery check. Each die is calibrated during wafer sort using a reference light source by a computer controlled metal link blowing technique. The chip is mounted in an 8-pin DIL package, Figure 4, which is molded in a clear compound. A small recess is formed in the package t o allow a light filter to be convenientlyinserted, thereby reducing the infrared response. A second lay-er of aluminum is used on the die t o shield the low level control circuitry from the incident light. Current was used as the analog of scene brightness because of the dynamic range and compatibility with bipolar circuitry. Special processing was developed to provide a blue-enhanced photodiode and transistors with good hFE holdup to handle the low level currents. A shallow photodlode junction was created by use of ion implantation to boost the normalized conversion efficiency to 60% in the visible light range. Low temperature processing and anneals,provide typical NPN hFE s of 100 and PNP hFE s of 50 at 1OnA collector current, while simultaneouslyholding junction leakages t o less than 1pA at room temperature. The filtered scene illumination is linearly convertcd t o current in the photodiode. The input differential amplifier, Figure 2, biases this device and replicates the photocurrent in a multiplicity of outputs. For near zero leakage a bias of 0V is needed, but a requirement that the shutter time out in total darkness necessitated a circuit which encourages the diode t o provide some limited dark current. The diodes at the noninverting input arc fixed biased whereas those in series with the photodiode carry I), (-4nA/Fc). Should I x 0, the latter diodes have n o voltage drop and the photodiode would approach a 1 V reverse bias. This stimulates leakage currcnt which increases the diode drops and tends to minimize and thereby regulate the leakage. Photodiode current, whether thermal or light induced, is provided by the upper PNPs through the action of the loop. The Ib of the NPN at the inverting input represents an error source which is reduced to less than 1% by adaptively biasing the tail current of the differential amplifier. This light dependent biasing technique improves the transient response of the loop, which is necessary .to realize proper exposure time when light is returned from a flash-illuminated subject; earlier cameras, which used the slower CdS cell, could not respond to this rqturncd light and would therefore produce an overexposed picture. Sufficient loop gain is provided t o insure linearity over the incident light range of in","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123725361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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