Architecture enhancements in 65nm SOTB power reconfigurable FPGA by fine-grained body biasing

Abstract

In the past, we developed 65nm SOTB power reconfigurable FPGAs by fine-grained body biasing composed of only elemental circuits such as LUT, DFF and MUX. This paper describes the architecture enhancements in the power reconfigurable FPGA including three key points such as the FPGA tile architecture optimization, reconfigurable clock gating scheme and 256kb RAM block implementation.