Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804404
C. Fenouillet-Béranger, P. Batude, L. Brunet, V. Mazzocchi, C-M. V. Lu, F. Deprat, J. Micout, M.-P. Samson, B. Previtali, P. Besombes, N. Rambal, V. Lapras, F. Andrieu, O. Billoint, M. Brocard, S. Thuries, G. Cibrario, P. Acosta-Alba, B. Mathieu, S. Kerdilès, F. Nemouchi, C. Arvet, P. Besson, V. Loup, R. Gassilloud, X. Garros, C. Leroux, V. Beugin, C. Guérin, D. Benoit, L. Pasini, J. Hartmann, M. Vinet
In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.
{"title":"Recent advances in low temperature process in view of 3D VLSI integration","authors":"C. Fenouillet-Béranger, P. Batude, L. Brunet, V. Mazzocchi, C-M. V. Lu, F. Deprat, J. Micout, M.-P. Samson, B. Previtali, P. Besombes, N. Rambal, V. Lapras, F. Andrieu, O. Billoint, M. Brocard, S. Thuries, G. Cibrario, P. Acosta-Alba, B. Mathieu, S. Kerdilès, F. Nemouchi, C. Arvet, P. Besson, V. Loup, R. Gassilloud, X. Garros, C. Leroux, V. Beugin, C. Guérin, D. Benoit, L. Pasini, J. Hartmann, M. Vinet","doi":"10.1109/S3S.2016.7804404","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804404","url":null,"abstract":"In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126392441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804385
F. Bashir, S. Loan, Asim M. Murshid, A. Alamoud
In this work, we propose a novel charge plasma based partial ground plane selective buried oxide MOSFET (CP-PGP-SELBOX-MOSFET). In the proposed device source, drain regions and the partial ground planes (PGPs) have been realized by using metals of different work-functions and not by the conventional method of doping. A two dimensional (2D) simulation study has revealed that the magnitude of the short-channel effects (SCEs) have got significantly reduced in the proposed device in comparison to the conventional one. Further, it has been observed that ION/IOFF ratio and subthreshold slope (SS) in the proposed device has been improved significantly in comparison to conventional SELBOX MOSFET. Further, the proposed device is free from doping related issues and can be fabricated at low temperature, as it does not employ the conventional ion implantation for realizing various regions.
{"title":"Charge plasma based partial-ground-plane-MOSFET on selective buried oxide (SELBOX)","authors":"F. Bashir, S. Loan, Asim M. Murshid, A. Alamoud","doi":"10.1109/S3S.2016.7804385","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804385","url":null,"abstract":"In this work, we propose a novel charge plasma based partial ground plane selective buried oxide MOSFET (CP-PGP-SELBOX-MOSFET). In the proposed device source, drain regions and the partial ground planes (PGPs) have been realized by using metals of different work-functions and not by the conventional method of doping. A two dimensional (2D) simulation study has revealed that the magnitude of the short-channel effects (SCEs) have got significantly reduced in the proposed device in comparison to the conventional one. Further, it has been observed that ION/IOFF ratio and subthreshold slope (SS) in the proposed device has been improved significantly in comparison to conventional SELBOX MOSFET. Further, the proposed device is free from doping related issues and can be fabricated at low temperature, as it does not employ the conventional ion implantation for realizing various regions.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132964573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804376
M. Brocard, R. Boumchedda, J. Noel, K. Akyel, B. Giraud, E. Beigné, D. Turgis, S. Thuries, G. Berhault, O. Billoint
In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell offers 30% footprint reduction compared to the planar 6T SRAM bitcell in 14nm FD-SOI technology.
{"title":"High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology","authors":"M. Brocard, R. Boumchedda, J. Noel, K. Akyel, B. Giraud, E. Beigné, D. Turgis, S. Thuries, G. Berhault, O. Billoint","doi":"10.1109/S3S.2016.7804376","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804376","url":null,"abstract":"In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell offers 30% footprint reduction compared to the planar 6T SRAM bitcell in 14nm FD-SOI technology.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130010372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804377
W. Schwarzenbach, F. Allibert, C. Le Royer, L. Grenouillet, C. Malaquin, C. Bertrand-Giuliani, F. Boedt, S. Loubriat, C. Michau, D. Parissi, B. Nguyen
SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) [1] and ultra-low power Fully Depleted (FDSOI) [2], the two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology [3]. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.
{"title":"Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD","authors":"W. Schwarzenbach, F. Allibert, C. Le Royer, L. Grenouillet, C. Malaquin, C. Bertrand-Giuliani, F. Boedt, S. Loubriat, C. Michau, D. Parissi, B. Nguyen","doi":"10.1109/S3S.2016.7804377","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804377","url":null,"abstract":"SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) [1] and ultra-low power Fully Depleted (FDSOI) [2], the two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology [3]. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121807381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804378
J. Auerhammer, C. Hartig, K. Wendt, R. van Oostrum, G. Pfeiffer, S. Bayer, B. Srocka
Fully depleted silicon-on-insulator (FD-SOI) wafers with very thin Si top layers in the range of ten nanometers have to fulfill very strict uniformity requirements in the Å range across the wafer for the latest CMOS technologies based on 22nm technology. Hereby, the thickness variation of the complete Si layer defining the body thickness of the transistor and thus the device properties have to be determined at not only a few locations of the wafer but a full lateral characterization is desirable. We have used differential reflective microscopy (DRM) in low-resolution mode for full-wafer maps and high-resolution mode at discrete locations to characterize the SOI thickness variation. Full wafer maps with DRM provide higher resolution than ellipsometry and can be used to control SOI manufacturing processes. We compare SOI thickness variation obtained from high-resolution measurements to ITRS roadmap requirements.
{"title":"Silicon thickness variation of FD-SOI wafers investigated by differential reflective microscopy","authors":"J. Auerhammer, C. Hartig, K. Wendt, R. van Oostrum, G. Pfeiffer, S. Bayer, B. Srocka","doi":"10.1109/S3S.2016.7804378","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804378","url":null,"abstract":"Fully depleted silicon-on-insulator (FD-SOI) wafers with very thin Si top layers in the range of ten nanometers have to fulfill very strict uniformity requirements in the Å range across the wafer for the latest CMOS technologies based on 22nm technology. Hereby, the thickness variation of the complete Si layer defining the body thickness of the transistor and thus the device properties have to be determined at not only a few locations of the wafer but a full lateral characterization is desirable. We have used differential reflective microscopy (DRM) in low-resolution mode for full-wafer maps and high-resolution mode at discrete locations to characterize the SOI thickness variation. Full wafer maps with DRM provide higher resolution than ellipsometry and can be used to control SOI manufacturing processes. We compare SOI thickness variation obtained from high-resolution measurements to ITRS roadmap requirements.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124510795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804396
Chang-Hung Yu, P. Su, C. Chuang
2-D transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) are very attractive for future ultimately scaled low-power CMOS devices owing to their atomic-scale thickness, adequate band-gap, and pristine surface (without dangling bonds) [1-3]. Our previous study [4] has evaluated the stability of MoS2-n/WSe2-p SRAMs with planar technology. However, the process complexity of heterogeneous integration of distinct materials for n/p-FETs can become a concern. Monolithic 3-D integration [5] offers the possibility to independently optimize the n-FETs and p-FETs at distinct tiers. It has also been envisioned [6] that monolithic 3-D integration combined with the extremely scaled TMD devices may offer the ultimate solution for future ultra-high density ICs and SRAMs (Fig. 1(c)).
{"title":"Stability optimization of monolithic 3-D MoS2-n/WSe2-p SRAM cells for superthreshold and near-/sub-threshold applications","authors":"Chang-Hung Yu, P. Su, C. Chuang","doi":"10.1109/S3S.2016.7804396","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804396","url":null,"abstract":"2-D transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) are very attractive for future ultimately scaled low-power CMOS devices owing to their atomic-scale thickness, adequate band-gap, and pristine surface (without dangling bonds) [1-3]. Our previous study [4] has evaluated the stability of MoS2-n/WSe2-p SRAMs with planar technology. However, the process complexity of heterogeneous integration of distinct materials for n/p-FETs can become a concern. Monolithic 3-D integration [5] offers the possibility to independently optimize the n-FETs and p-FETs at distinct tiers. It has also been envisioned [6] that monolithic 3-D integration combined with the extremely scaled TMD devices may offer the ultimate solution for future ultra-high density ICs and SRAMs (Fig. 1(c)).","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126654500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804405
S. Samal, D. Nayak, M. Ichihashi, S. Banna, S. Lim
In this paper, we conduct a comprehensive design comparison of 2D ICs, monolithic 3D ICs and TSV-based 3D ICs using a silicon-validated 14nm FinFET foundry technology and commercial quality designs. Through full-chip layouts and sign-off analysis using commercial-grade tools, the potential of monolithic 3D IC is explored and validated in terms of power, performance and area against that of TSV-based 3D ICs and 2D ICs.
{"title":"Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology","authors":"S. Samal, D. Nayak, M. Ichihashi, S. Banna, S. Lim","doi":"10.1109/S3S.2016.7804405","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804405","url":null,"abstract":"In this paper, we conduct a comprehensive design comparison of 2D ICs, monolithic 3D ICs and TSV-based 3D ICs using a silicon-validated 14nm FinFET foundry technology and commercial quality designs. Through full-chip layouts and sign-off analysis using commercial-grade tools, the potential of monolithic 3D IC is explored and validated in terms of power, performance and area against that of TSV-based 3D ICs and 2D ICs.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131533273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804407
R. Choi, Hyun‐Yong Yu, Hyungsub Kim, H. Ryu, H. Bae, K. K. Choi, Yong-Won Cha, C. Choi
We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (<; 450°C), low temperature (<; 550°C) in-situ doped S/D selective SiGe epi process, low temperature (<; 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.
{"title":"Bonding based channel transfer and low temperature process for monolithic 3D integration platform development","authors":"R. Choi, Hyun‐Yong Yu, Hyungsub Kim, H. Ryu, H. Bae, K. K. Choi, Yong-Won Cha, C. Choi","doi":"10.1109/S3S.2016.7804407","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804407","url":null,"abstract":"We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (<; 450°C), low temperature (<; 550°C) in-situ doped S/D selective SiGe epi process, low temperature (<; 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129384069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804403
Soundous Chairat, E. Beigné, Florent Berthier, I. Miro-Panadès, M. Belleville
The paper describes a new asynchronous communication network for reconfiguration of adaptive Wireless Sensor Network (WSN) nodes. The use of adaptive blocks is motivated by the need to increase the performance of the node while being energy efficient. They are able to adapt their performance to the environment, the energy budget and the task. The purpose of the proposed communication network is to handle control signals, both in sleep and working mode of the node at a low energy cost. We show that we can achieve a 0.07pJ/bit in energy per bit and 1.1ns/bit in latency in a 28nm FDSOI technology at 0.6V in asynchronous QDI logic.
{"title":"Ultra low energy FDSOI asynchronous reconfiguration network for an IoT wireless sensor network node","authors":"Soundous Chairat, E. Beigné, Florent Berthier, I. Miro-Panadès, M. Belleville","doi":"10.1109/S3S.2016.7804403","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804403","url":null,"abstract":"The paper describes a new asynchronous communication network for reconfiguration of adaptive Wireless Sensor Network (WSN) nodes. The use of adaptive blocks is motivated by the need to increase the performance of the node while being energy efficient. They are able to adapt their performance to the environment, the energy budget and the task. The purpose of the proposed communication network is to handle control signals, both in sleep and working mode of the node at a low energy cost. We show that we can achieve a 0.07pJ/bit in energy per bit and 1.1ns/bit in latency in a 28nm FDSOI technology at 0.6V in asynchronous QDI logic.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114192710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804406
M. Amir, D. Kim, J. Kung, D. Lie, S. Yalamanchili, S. Mukhopadhyay
3D integration provides opportunities to design high-bandwidth and low-power CMOS image sensors (CIS) [1–4]. The 3D stacking of pixel tier, peripheral tier, memory tier(s), and compute tier(s) enables high degree of parallel processing. Also, each tier can be designed in different technology nodes (heterogeneous integration) to further improve power-efficiency. This paper presents a case study of a smart 3D image sensor with integrated neuro-inspired computing for intelligent vision processing. Hardware acceleration of neuro-inspired computing has received much attention in recent years for recognition and classification [5]. We present the physical design of NeuroSensor, a 3D CIS with an integrated convolutional neural network (CNN) accelerator. The rationale for our approach is that 3D integration of sensor, memory, and computing will effectively harness the inherent parallelism in neural algorithms. We design the NeuroSensor considering different complexities of CNN platform, ranging from only feature extraction to complete classification, and study the trade-offs between complexity, performance, and power.
{"title":"NeuroSensor: A 3D image sensor with integrated neural accelerator","authors":"M. Amir, D. Kim, J. Kung, D. Lie, S. Yalamanchili, S. Mukhopadhyay","doi":"10.1109/S3S.2016.7804406","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804406","url":null,"abstract":"3D integration provides opportunities to design high-bandwidth and low-power CMOS image sensors (CIS) [1–4]. The 3D stacking of pixel tier, peripheral tier, memory tier(s), and compute tier(s) enables high degree of parallel processing. Also, each tier can be designed in different technology nodes (heterogeneous integration) to further improve power-efficiency. This paper presents a case study of a smart 3D image sensor with integrated neuro-inspired computing for intelligent vision processing. Hardware acceleration of neuro-inspired computing has received much attention in recent years for recognition and classification [5]. We present the physical design of NeuroSensor, a 3D CIS with an integrated convolutional neural network (CNN) accelerator. The rationale for our approach is that 3D integration of sensor, memory, and computing will effectively harness the inherent parallelism in neural algorithms. We design the NeuroSensor considering different complexities of CNN platform, ranging from only feature extraction to complete classification, and study the trade-offs between complexity, performance, and power.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127112949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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