A 4 bit Quantum Voltage Comparator based flash ADC for low noise applications

Abstract

Analog to Digital Converter (ADC) is an essential part of a mixed signal circuit design, which acts as a bridge between naturally occurring analog signals and digital signals. It has been a continuous effort of the researchers to reduce or keep the noise constant along with the level of advancement made in the field of mixed signal circuit design to increase the speed. This work has been intended towards modification of Quantum Voltage Comparator (QVC) in a 4 bit flash ADC design which results in the reduction of linearity along with noise. The 2×1 multiplexer based decoder in ADC increases the speed of the circuit. QVC is a cascading of two differential comparators as a single comparator with systematically varying sizes of NMOS pair, which eliminates the resistor ladder circuit in a conventional flash ADC. In this work, the modified QVC based flash ADC works on a single input voltage. It has been simulated in GPDK 180 nm CADENCE VIRTUOSO platform with a supply voltage of 1.8 V. This proposed flash ADC design results in a significant drop in noise, yielding an SNR value of 25.4 dB with a sampling rate of 5.12 GS/s with a power consumption of 4.19 mW.