Tsuyoshi Takahashi, Satoshi Kojima, O. Yamashiro, Kazuhiko Eguchi, H. Fukuda
{"title":"An MOS Digital Network Model on a Modified Thevenin Equivalent for Logic Simulation","authors":"Tsuyoshi Takahashi, Satoshi Kojima, O. Yamashiro, Kazuhiko Eguchi, H. Fukuda","doi":"10.1109/DAC.1984.1585851","DOIUrl":null,"url":null,"abstract":"A novel analytical model of MOS digital networks, which is based on a modified Thevenin equivalent, is described. The model can handle all the primary circuits inherent in MOS technology, such as transistor logics, wired-ORs, tri-state circuits, charge-share operation, and bidirectional pass transistors etc., with precise estimation of delay time. The model has been implemented in a logic/fault simulator, named HASL-GT. Performance of 4 to 10 k events/sec has been obtained on HITAC M-200H(8MIPS). Fault simulation capability has also been implemented using the concurrent method.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st Design Automation Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1984.1585851","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A novel analytical model of MOS digital networks, which is based on a modified Thevenin equivalent, is described. The model can handle all the primary circuits inherent in MOS technology, such as transistor logics, wired-ORs, tri-state circuits, charge-share operation, and bidirectional pass transistors etc., with precise estimation of delay time. The model has been implemented in a logic/fault simulator, named HASL-GT. Performance of 4 to 10 k events/sec has been obtained on HITAC M-200H(8MIPS). Fault simulation capability has also been implemented using the concurrent method.
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