W. Yueh, S. Chatterjee, A. Trivedi, S. Mukhopadhyay
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引用次数: 3
Abstract
This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model. The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.
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