Reference model based RTL verification: an integrated approach

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI:10.1109/HLDVT.2004.1431221

W. Hung, N. Narasimhan

引用次数: 10

Abstract

We present an approach that makes reference model based formal verification both complete and practical in an industrial setting. This paper describes a novel approach to conduct this exercise, by seamlessly integrating formal equivalence verification (FEV) techniques within a verification flow suited to formal property verification (FPV). This enables us to take full advantage of the rich expressive power of temporal specification languages and help guide the FEV tools so as to enable reference model verification to an extent that was never attempted before. We have successfully applied our approach to challenging verification problems at Intel/spl reg/.

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基于参考模型的RTL验证:一种集成方法

我们提出了一种方法，使基于参考模型的形式验证在工业环境中既完整又实用。本文描述了一种新的方法，通过在适合于形式属性验证(FPV)的验证流中无缝地集成形式等效验证(FEV)技术来进行该练习。这使我们能够充分利用时间规范语言丰富的表达能力，并帮助指导FEV工具，从而使参考模型验证达到以前从未尝试过的程度。我们已经成功地将我们的方法应用于Intel/spl reg/上具有挑战性的验证问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

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