Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431251
Y. Sha, M. Lee, C. Liu
In order to verify the integration of digital circuits and analog circuits in a SOC design, HDL-A languages are proposed to describe analog circuits such that they can be simulated together with the digital circuits described in HDL code. For digital circuits, coverage-driven approach has been widely used to verify the quality of HDL designs. However, for analog models, there are still no suitable solutions to gauge their quality. Therefore, in this paper, we will first discuss the feasibility and its meaning of applying some existing coverage metrics to Verilog-A code. We also propose a new coverage metric, frequency coverage, for checking the completeness of the frequency response in Verilog-A designs. Using this coverage metric as an assistant to existing code coverage metrics, we can have more confidence on the correctness of the Verilog-A descriptions at different situations.
{"title":"On code coverage measurement for Verilog-A","authors":"Y. Sha, M. Lee, C. Liu","doi":"10.1109/HLDVT.2004.1431251","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431251","url":null,"abstract":"In order to verify the integration of digital circuits and analog circuits in a SOC design, HDL-A languages are proposed to describe analog circuits such that they can be simulated together with the digital circuits described in HDL code. For digital circuits, coverage-driven approach has been widely used to verify the quality of HDL designs. However, for analog models, there are still no suitable solutions to gauge their quality. Therefore, in this paper, we will first discuss the feasibility and its meaning of applying some existing coverage metrics to Verilog-A code. We also propose a new coverage metric, frequency coverage, for checking the completeness of the frequency response in Verilog-A designs. Using this coverage metric as an assistant to existing code coverage metrics, we can have more confidence on the correctness of the Verilog-A descriptions at different situations.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122483843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431245
S. Suhaib, D. Mathaikutty, S. Shukla
In this paper, we analyze the effect of ordering linear time properties while using the Extreme Formal Modeling (XFM) methodology in building "prescriptive formal models" (PFM). PFMs are formal models built incrementally by adding user stories and are used as specification golden models. In our methodology, the user stories are captured in Linear Time Temporal Logic (LTL). A more expressive logic or formalism could be used for describing the user stories as well. During incremental model building, the PFMs often blow up in size in terms of the state space, and the main tenet of XFM being regressive model checking, blown up models often make it impossible to carry out the XFM methodology. Here, we propose property ordering hueristics to circumvent this problem. We compare these hueristics with: (i) no specific ordering of user stories (standard approach), (ii) sorting of the user stories based on a weighting scheme (property based sorting), and (Hi) predicate based sorting of user stories based on an eliminative scheme (predicate based sorting). We show that the predicate based sorting scheme is the most effective way to carry-out XFM model building. We illustrate the schemes and the comparison by modeling a monitor for the ISA bus and for the arbitration phase of Pentium Pro processor's bus using the Cadence SMV. We also provide an algorithm for the predicate based sorting that yields the best control on the increments in model size.
{"title":"Effects of property ordering in an incremental formal modeling methodology","authors":"S. Suhaib, D. Mathaikutty, S. Shukla","doi":"10.1109/HLDVT.2004.1431245","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431245","url":null,"abstract":"In this paper, we analyze the effect of ordering linear time properties while using the Extreme Formal Modeling (XFM) methodology in building \"prescriptive formal models\" (PFM). PFMs are formal models built incrementally by adding user stories and are used as specification golden models. In our methodology, the user stories are captured in Linear Time Temporal Logic (LTL). A more expressive logic or formalism could be used for describing the user stories as well. During incremental model building, the PFMs often blow up in size in terms of the state space, and the main tenet of XFM being regressive model checking, blown up models often make it impossible to carry out the XFM methodology. Here, we propose property ordering hueristics to circumvent this problem. We compare these hueristics with: (i) no specific ordering of user stories (standard approach), (ii) sorting of the user stories based on a weighting scheme (property based sorting), and (Hi) predicate based sorting of user stories based on an eliminative scheme (predicate based sorting). We show that the predicate based sorting scheme is the most effective way to carry-out XFM model building. We illustrate the schemes and the comparison by modeling a monitor for the ISA bus and for the arbitration phase of Pentium Pro processor's bus using the Cadence SMV. We also provide an algorithm for the predicate based sorting that yields the best control on the increments in model size.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131469520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431250
Ahmad A. Al-Yamani, E. McCluskey
Using complex (high-level) gates, such as multiplexers, full adders, etc., for automatic test pattern generation (ATPG) has several advantages. It makes A TPG faster and potentially reduces the size of the test set that needs to be applied. A variety of other techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This paper presents data obtained from applying a variety of test sets on the ELF35 test chip and recording the test escapes. The data presented show the test quality effect of using complex gates as fault sites. The paper also shows the impact of test compaction and reduced fault coverage on the test quality.
{"title":"Test quality for high level structural test","authors":"Ahmad A. Al-Yamani, E. McCluskey","doi":"10.1109/HLDVT.2004.1431250","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431250","url":null,"abstract":"Using complex (high-level) gates, such as multiplexers, full adders, etc., for automatic test pattern generation (ATPG) has several advantages. It makes A TPG faster and potentially reduces the size of the test set that needs to be applied. A variety of other techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This paper presents data obtained from applying a variety of test sets on the ELF35 test chip and recording the test escapes. The data presented show the test quality effect of using complex gates as fault sites. The paper also shows the impact of test compaction and reduced fault coverage on the test quality.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133416912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431272
Gary Smith
In 1996 a group of EDA Industry experk, primarily from the Formal Verification field, looked at the future of verification. The first conclusion was that there were no silver bullets. The answer to the Verification Crisis would have to be a suit of tools, each attacking the problem from a different perspective. Out of that discussion came the concept of the Intelligent Test bench. The idea of the Intelligent Test bench was a test bench that would look at a design, parfition if into verification blocks and then invoke the verification tool most suited for the particular verification challenge. To do this if was assumed that it would be necessary to use an ES Level Verification tool to provide the view of the design for proper partitioning. What actually happened was something a bit different.
{"title":"What happened to the intelligent test bench?","authors":"Gary Smith","doi":"10.1109/HLDVT.2004.1431272","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431272","url":null,"abstract":"In 1996 a group of EDA Industry experk, primarily from the Formal Verification field, looked at the future of verification. The first conclusion was that there were no silver bullets. The answer to the Verification Crisis would have to be a suit of tools, each attacking the problem from a different perspective. Out of that discussion came the concept of the Intelligent Test bench. The idea of the Intelligent Test bench was a test bench that would look at a design, parfition if into verification blocks and then invoke the verification tool most suited for the particular verification challenge. To do this if was assumed that it would be necessary to use an ES Level Verification tool to provide the view of the design for proper partitioning. What actually happened was something a bit different.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132000885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431252
Xiao Liu, M. Hsiao
This paper presents a new approach on identifying functionally untestable transition faults in nonscan sequential circuits. We formulate a new dominance relationship for transition faults and use it to identify more sequentially untestable transition faults. The proposed method consists of two phases: first, a large number of functionally untestable transition faults is identified by a fault-independent sequential logic implications implicitly crossing multiple time-frames, and the identified untestable faults are classified into three conflict categories. Next, additional functionally untestable transition faults are identified by dominance relationships from the previous identified untestable transition faults. The experimental results for ISCAS89 sequential benchmark circuits showed that our approach can quickly identify many more functionally untestable transition faults than previously reported.
{"title":"On identifying functionally untestable transition faults","authors":"Xiao Liu, M. Hsiao","doi":"10.1109/HLDVT.2004.1431252","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431252","url":null,"abstract":"This paper presents a new approach on identifying functionally untestable transition faults in nonscan sequential circuits. We formulate a new dominance relationship for transition faults and use it to identify more sequentially untestable transition faults. The proposed method consists of two phases: first, a large number of functionally untestable transition faults is identified by a fault-independent sequential logic implications implicitly crossing multiple time-frames, and the identified untestable faults are classified into three conflict categories. Next, additional functionally untestable transition faults are identified by dominance relationships from the previous identified untestable transition faults. The experimental results for ISCAS89 sequential benchmark circuits showed that our approach can quickly identify many more functionally untestable transition faults than previously reported.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114745196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431267
M. Fujita
In this paper we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed "attribute statements" in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are presented as well.
{"title":"On equivalence checking between behavioral and RTL descriptions","authors":"M. Fujita","doi":"10.1109/HLDVT.2004.1431267","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431267","url":null,"abstract":"In this paper we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed \"attribute statements\" in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are presented as well.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125072299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431247
S. Abdi, D. Gajski
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for checking functional equivalence of system level models, before and after the distribution of behaviors in the specification over components in the platform architecture. We derive a control flow graph from models written in system level design languages (SLDLs) and reduce it to a normal form representation using well defined rules. Two models having identical normal form are shown to be functionally equivalent. An equivalence checker based on the above concept is used to automatically check if the architecture level model is functionally equivalent to the specification model. As a result, the models generated for various mapping decisions do not have to be reverified using costly simulations.
{"title":"Model validation for mapping specification behaviors to processing elements","authors":"S. Abdi, D. Gajski","doi":"10.1109/HLDVT.2004.1431247","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431247","url":null,"abstract":"Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for checking functional equivalence of system level models, before and after the distribution of behaviors in the specification over components in the platform architecture. We derive a control flow graph from models written in system level design languages (SLDLs) and reduce it to a normal form representation using well defined rules. Two models having identical normal form are shown to be functionally equivalent. An equivalence checker based on the above concept is used to automatically check if the architecture level model is functionally equivalent to the specification model. As a result, the models generated for various mapping decisions do not have to be reverified using costly simulations.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125175223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431265
P. Murthy, S. Rajan, K. Takayama
We describe a methodology for designing, testing, and verifying hardware designs from a high level of abstraction, using a visual formalism based on hierarchical message sequence charts. We develop a method for generating behaviors and monitors automatically from this high level description, and using it to validate actual hardware implementations developed by design teams. We apply our methodology to the design of a PCl-Express switch, and show that the methodology is useful in finding many design errors. We develop an enhanced hMSC language that can be much better suited for describing complex standards and protocols like the PCI-express.
{"title":"High level hardware validation using hierarchical message sequence charts","authors":"P. Murthy, S. Rajan, K. Takayama","doi":"10.1109/HLDVT.2004.1431265","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431265","url":null,"abstract":"We describe a methodology for designing, testing, and verifying hardware designs from a high level of abstraction, using a visual formalism based on hierarchical message sequence charts. We develop a method for generating behaviors and monitors automatically from this high level description, and using it to validate actual hardware implementations developed by design teams. We apply our methodology to the design of a PCl-Express switch, and show that the methodology is useful in finding many design errors. We develop an enhanced hMSC language that can be much better suited for describing complex standards and protocols like the PCI-express.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431266
D. Gil, J. Gracia, J. Baraza, P. Gil
Modern processors tend to increase the number of registers, being part of them not accessible by the instruction set. Traditionally, the effect of faults in these hidden registers has not been considered during system validation using fault injection. In this paper, a study of the importance of faults in hidden registers is performed. Firstly, we have analysed the sensitivity of hidden registers to faults in combinational logic. In a second phase, we have analysed the impact of the faults occurred in hidden registers on system behaviour. A broad set of permanent and transient faults have been injected into the models of two typical commercial microcontrollers, using a VHDL-based fault injection tool developed by our research group. The results obtained indicate that the incidence of hidden registers is not negligible, and in some cases is even notable. This fact suggests that widely used fault injection techniques such as SWIFI could not be enough to perform a full and representative validation of modern processors, and it would be necessary to complement with other fault injection techniques that have a higher degree of accessibility.
{"title":"Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques","authors":"D. Gil, J. Gracia, J. Baraza, P. Gil","doi":"10.1109/HLDVT.2004.1431266","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431266","url":null,"abstract":"Modern processors tend to increase the number of registers, being part of them not accessible by the instruction set. Traditionally, the effect of faults in these hidden registers has not been considered during system validation using fault injection. In this paper, a study of the importance of faults in hidden registers is performed. Firstly, we have analysed the sensitivity of hidden registers to faults in combinational logic. In a second phase, we have analysed the impact of the faults occurred in hidden registers on system behaviour. A broad set of permanent and transient faults have been injected into the models of two typical commercial microcontrollers, using a VHDL-based fault injection tool developed by our research group. The results obtained indicate that the incidence of hidden registers is not negligible, and in some cases is even notable. This fact suggests that widely used fault injection techniques such as SWIFI could not be enough to perform a full and representative validation of modern processors, and it would be necessary to complement with other fault injection techniques that have a higher degree of accessibility.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129602870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-10DOI: 10.1109/HLDVT.2004.1431223
P. Peranandam, R. Weiss, Jürgen Ruf, T. Kropf, W. Rosenstiel
Current statistics attribute up to 75% of the overall design costs of digital hardware and embedded system development to the verification task. In recent years, the trend to augment functional with formal verification tries to alleviate this problem. Efficient property checking algorithms allow automatic verification of middle-sized designs nowadays. However, the steadily increasing design sizes still leave verification the major bottleneck, because formal methodologies do not yet scale to very large designs. In this paper we present the formal verification tool SymC based on forward state space traversal and so-called AR-automata for property checking, both internally represented with BDDs. Furthermore, we introduce a new methodology called dynamic guiding. This methodology best suits multimodule concurrent finite state machine (FSM) designs. The aim of guiding is to reduce the intermediate and final BDD size, which in turn makes this verification technique applicable to larger designs. Our approach exploits abstract information of the design in the form of regular expressions and effectively guides the symbolic traversal depending on the verified property.
{"title":"Dynamic guiding of bounded property checking","authors":"P. Peranandam, R. Weiss, Jürgen Ruf, T. Kropf, W. Rosenstiel","doi":"10.1109/HLDVT.2004.1431223","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431223","url":null,"abstract":"Current statistics attribute up to 75% of the overall design costs of digital hardware and embedded system development to the verification task. In recent years, the trend to augment functional with formal verification tries to alleviate this problem. Efficient property checking algorithms allow automatic verification of middle-sized designs nowadays. However, the steadily increasing design sizes still leave verification the major bottleneck, because formal methodologies do not yet scale to very large designs. In this paper we present the formal verification tool SymC based on forward state space traversal and so-called AR-automata for property checking, both internally represented with BDDs. Furthermore, we introduce a new methodology called dynamic guiding. This methodology best suits multimodule concurrent finite state machine (FSM) designs. The aim of guiding is to reduce the intermediate and final BDD size, which in turn makes this verification technique applicable to larger designs. Our approach exploits abstract information of the design in the form of regular expressions and effectively guides the symbolic traversal depending on the verified property.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131355119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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