An ISA-level Accurate Fault Simulator for System-level Fault Analysis

Abstract

Shrinking feature sizes and cell capacitances, lower operation voltages, and higher operation speeds intensify the influences of radiation-induced soft-errors. To guarantee the functional safety of electronic systems, designers need effective techniques to evaluate designs under errors. Fault injection is one of the standard assessment tools for system dependability. However, because traditional RTL fault simulation has become too slow for modern complex systems, we need abstraction models for early-stage system reliability analysis and design. In this paper, we present an accurate reliability assessment SystemC fault simulator. It features a dynamic mechanism for injecting faults and analyzing the produced errors to evaluate possible fault detection and tolerance designs. Our experimental results show that our simulator can achieve 470x speedup on accurate architecture register fault simulation, validated with the RTL model.