Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301550
Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, A. Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, K. Hatayama, Haruo Kobayashi
This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.
{"title":"Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers","authors":"Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, A. Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, K. Hatayama, Haruo Kobayashi","doi":"10.1109/ATS49688.2020.9301550","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301550","url":null,"abstract":"This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301575
Yuqian Pan, Haichun Zhang, Mingyang Gong, Zhenglin Liu
Wear-out has been a critical reliability problem in NAND flash memory. As executing repeated program and erase operations on the NAND flash chips, the number of errors increases and ultimately exceeds the ECC capability. In previous work, error characteristics of flash wear-out are observed by endurance tests on a single type of NAND flash memory. We wonder if the experimental results cover the entire error characteristics of NAND flash memory. In this paper, we tested more than 20 types of NAND flash chips with different vendors and structures and presented an overlook of test results. Through the test results, we found an unexpected error-explosion phenomenon that errors of flash blocks first increase over several cycles and then reach a high value without warning. We analyzed the features of the error-explosion and explored its influence on operation time. And we propose an error-explosion prediction scheme to find the blocks that will occur an error-explosion in the next 1000 P/E cycles. The block identifying operation is realized by the machine-learning model. The performance of six machine-learning methods is compared. The results demonstrate that the Decision Trees and Bagged Classification Trees have the best accuracy.
{"title":"Unexpected Error Explosion in NAND Flash Memory: Observations and Prediction Scheme","authors":"Yuqian Pan, Haichun Zhang, Mingyang Gong, Zhenglin Liu","doi":"10.1109/ATS49688.2020.9301575","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301575","url":null,"abstract":"Wear-out has been a critical reliability problem in NAND flash memory. As executing repeated program and erase operations on the NAND flash chips, the number of errors increases and ultimately exceeds the ECC capability. In previous work, error characteristics of flash wear-out are observed by endurance tests on a single type of NAND flash memory. We wonder if the experimental results cover the entire error characteristics of NAND flash memory. In this paper, we tested more than 20 types of NAND flash chips with different vendors and structures and presented an overlook of test results. Through the test results, we found an unexpected error-explosion phenomenon that errors of flash blocks first increase over several cycles and then reach a high value without warning. We analyzed the features of the error-explosion and explored its influence on operation time. And we propose an error-explosion prediction scheme to find the blocks that will occur an error-explosion in the next 1000 P/E cycles. The block identifying operation is realized by the machine-learning model. The performance of six machine-learning methods is compared. The results demonstrate that the Decision Trees and Bagged Classification Trees have the best accuracy.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114493337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301614
Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu
The development of integrated circuit technology is accompanied by potential threats. Malicious modifications to circuits, known as hardware Trojans, are major security concerns. This paper gives a survey of hardware Trojan detection methods towards gate-level netlists. The detection methods are divided into search-based, threshold-based, and machine learning-based ones. This paper compares and analyzes existing works from aspects of feature selection, data balancing techniques, classification criterion, detection range. The experimental results are also selected for comparison.
{"title":"Survey: Hardware Trojan Detection for Netlist","authors":"Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu","doi":"10.1109/ATS49688.2020.9301614","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301614","url":null,"abstract":"The development of integrated circuit technology is accompanied by potential threats. Malicious modifications to circuits, known as hardware Trojans, are major security concerns. This paper gives a survey of hardware Trojan detection methods towards gate-level netlists. The detection methods are divided into search-based, threshold-based, and machine learning-based ones. This paper compares and analyzes existing works from aspects of feature selection, data balancing techniques, classification criterion, detection range. The experimental results are also selected for comparison.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129924083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301568
Shao-Chun Hung, Yi-Chen Lu, S. Lim, K. Chakrabarty
Monolithic 3D (M3D) integration is an emerging technology that offers significant power, performance, and area benefits for integrated circuit (IC) design. However, a problem with the 3D power distribution network in such ICs is that it can lead to high power supply noise (PSN) during the capture cycles in at-speed scan testing for transition delay faults. Therefore, the failure of good chips (i.e., yield loss) resulting from the PSN-induced voltage droop is a major concern for M3D designs. In this paper, we first assess the PSN and voltage droop problems, and their impact on path delays for at-speed testing of benchmark M3D designs. Next, we present an analysis framework to identify test patterns that are most likely to lead to yield loss. We describe a test-pattern reshaping solution based on integer linear programming to make appropriate changes to the test patterns that cause yield loss. Simulation results for four M3D benchmarks highlight the effectiveness of the proposed solution.
{"title":"Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *","authors":"Shao-Chun Hung, Yi-Chen Lu, S. Lim, K. Chakrabarty","doi":"10.1109/ATS49688.2020.9301568","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301568","url":null,"abstract":"Monolithic 3D (M3D) integration is an emerging technology that offers significant power, performance, and area benefits for integrated circuit (IC) design. However, a problem with the 3D power distribution network in such ICs is that it can lead to high power supply noise (PSN) during the capture cycles in at-speed scan testing for transition delay faults. Therefore, the failure of good chips (i.e., yield loss) resulting from the PSN-induced voltage droop is a major concern for M3D designs. In this paper, we first assess the PSN and voltage droop problems, and their impact on path delays for at-speed testing of benchmark M3D designs. Next, we present an analysis framework to identify test patterns that are most likely to lead to yield loss. We describe a test-pattern reshaping solution based on integer linear programming to make appropriate changes to the test patterns that cause yield loss. Simulation results for four M3D benchmarks highlight the effectiveness of the proposed solution.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114832352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301557
I. Polian, J. Anders, Steffen Becker, P. Bernardi, K. Chakrabarty, N. Elhamawy, M. Sauer, A. Singh, M. Reorda, S. Wagner
System-level test, or SLT, is an increasingly important process step in today’s integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.
{"title":"Exploring the Mysteries of System-Level Test","authors":"I. Polian, J. Anders, Steffen Becker, P. Bernardi, K. Chakrabarty, N. Elhamawy, M. Sauer, A. Singh, M. Reorda, S. Wagner","doi":"10.1109/ATS49688.2020.9301557","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301557","url":null,"abstract":"System-level test, or SLT, is an increasingly important process step in today’s integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127740888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301546
Jian Hu, Yongyang Hu, Long Yu, Haitao Yang, Yun Kang, Jie Cheng
High-level synthesis (HLS) compiles a algorithmic description (C or C++) into a digital hardware implementation (VHDL or Verilog) through a sequence of transformations. However, the complex compiling process may introduce an error in the produced register-transfer level (RTL) implementation. Global common subexpression elimination (GCSE) as a commonly used code motion technique in the scheduling of HLS is an error-prone and complex process that need to be validated. In this paper, we propose an equivalence checking method to validate GCSE with non-common variables used in the rest code in the scheduling of HLS by enhancing the path equivalence criteria. The source and target programs are modeled using Finite State Machine with Datapath (FSMD) that is essentially a Control and Data Flow Graph (CDFG). The experimental results show that our method can indeed validate the GCSE with non-common variables used in the rest code in HLS which has not been solved in the existing papers.
{"title":"Validating GCSE in the scheduling of high-level synthesis","authors":"Jian Hu, Yongyang Hu, Long Yu, Haitao Yang, Yun Kang, Jie Cheng","doi":"10.1109/ATS49688.2020.9301546","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301546","url":null,"abstract":"High-level synthesis (HLS) compiles a algorithmic description (C or C++) into a digital hardware implementation (VHDL or Verilog) through a sequence of transformations. However, the complex compiling process may introduce an error in the produced register-transfer level (RTL) implementation. Global common subexpression elimination (GCSE) as a commonly used code motion technique in the scheduling of HLS is an error-prone and complex process that need to be validated. In this paper, we propose an equivalence checking method to validate GCSE with non-common variables used in the rest code in the scheduling of HLS by enhancing the path equivalence criteria. The source and target programs are modeled using Finite State Machine with Datapath (FSMD) that is essentially a Control and Data Flow Graph (CDFG). The experimental results show that our method can indeed validate the GCSE with non-common variables used in the rest code in HLS which has not been solved in the existing papers.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301603
Shengyu Duan, Peng Wang, G. Sai
Bias Temperature Instability (BTI) is one of the dominant CMOS aging mechanisms. It causes time-dependent variation, threatening circuit lifetime reliability. BTI-induced circuit errors are not detectable at the fabrication stage. On-line monitoring schemes are therefore necessary to capture the degradations during the operational time. Traditional aging monitoring techniques exhibit high implementation complexity and low stability. In this paper, we propose a BTI monitoring approach by simply tracking the start-up behavior of SRAM cells. SRAM is a widely used on-chip device in many applications. We study the impact of BTI for SRAM start-up values and age some cells in a manipulated manner. The BTI degradation is evaluated based on the number of SRAM cells starting with a certain value. This technique can be used to estimate the degradation for on-chip logic circuits without introducing additional circuitry, and thus has very low implementation complexity. We use an SRAM array with 1024 cells to estimate the degradations for multiple logic circuits, and show the average mean absolute percentage error as 8.48%. In addition, this technique is robust considering process, voltage and temperature variations.
{"title":"BTI Aging Monitoring based on SRAM Start-up Behavior","authors":"Shengyu Duan, Peng Wang, G. Sai","doi":"10.1109/ATS49688.2020.9301603","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301603","url":null,"abstract":"Bias Temperature Instability (BTI) is one of the dominant CMOS aging mechanisms. It causes time-dependent variation, threatening circuit lifetime reliability. BTI-induced circuit errors are not detectable at the fabrication stage. On-line monitoring schemes are therefore necessary to capture the degradations during the operational time. Traditional aging monitoring techniques exhibit high implementation complexity and low stability. In this paper, we propose a BTI monitoring approach by simply tracking the start-up behavior of SRAM cells. SRAM is a widely used on-chip device in many applications. We study the impact of BTI for SRAM start-up values and age some cells in a manipulated manner. The BTI degradation is evaluated based on the number of SRAM cells starting with a certain value. This technique can be used to estimate the degradation for on-chip logic circuits without introducing additional circuitry, and thus has very low implementation complexity. We use an SRAM array with 1024 cells to estimate the degradations for multiple logic circuits, and show the average mean absolute percentage error as 8.48%. In addition, this technique is robust considering process, voltage and temperature variations.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301531
F. Morishita, M. Otsuka, Wataru Saito
This paper proposes a novel circuit and technique for high accuracy measurement of analog-to-digital converters (ADCs) within a CMOS image sensor (CIS) chip. The evaluation of such ADCs has been a big challenge because optical signal source for CIS input is difficult to manage and control. The test circuit provides a dual path, one for normal operation and the other for applying external electrical input signal directly to ADC. This test path also has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics. This test circuit and technique enables the measurement of ADC characteristics directly from CIS chip. Measured result shows INL of 15 LSB, crosstalk of 20 LSB and accelerated column interference of 5 LSB. These measured results agreed with the designed values. With this straightforward circuit and technique, we confirmed the measurement accuracy of 14-bit.
{"title":"An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor","authors":"F. Morishita, M. Otsuka, Wataru Saito","doi":"10.1109/ATS49688.2020.9301531","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301531","url":null,"abstract":"This paper proposes a novel circuit and technique for high accuracy measurement of analog-to-digital converters (ADCs) within a CMOS image sensor (CIS) chip. The evaluation of such ADCs has been a big challenge because optical signal source for CIS input is difficult to manage and control. The test circuit provides a dual path, one for normal operation and the other for applying external electrical input signal directly to ADC. This test path also has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics. This test circuit and technique enables the measurement of ADC characteristics directly from CIS chip. Measured result shows INL of 15 LSB, crosstalk of 20 LSB and accelerated column interference of 5 LSB. These measured results agreed with the designed values. With this straightforward circuit and technique, we confirmed the measurement accuracy of 14-bit.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116891625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：