{"title":"Physical Insights on Junction Controllability for Improved Performance of Planar Trigate Tunnel FET as Capacitorless Dynamic Memory","authors":"Nupur Navlakha, A. Kranti","doi":"10.1109/SISPAD.2018.8551717","DOIUrl":null,"url":null,"abstract":"The work presents physical insights on the control of energy barriers at junctions of a planar trigate Tunnel FET (TFET) for dynamic memory applications. Results demonstrate the significance of electric field (EF) at each junction i.e. Source-Gate1 (S-G1), Drain-Gate2 (D-G2), and that between gates, evaluated through the energy barrier between G1-G2 (Eb) to improve Sense Margin (SM), Current Ratio (CR), speed (write time) and Retention Time (RT). The work highlights the impact of device parameters that aid to improve the performance metrics, and also reduce the associated trade-offs in dynamic memory.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2018.8551717","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The work presents physical insights on the control of energy barriers at junctions of a planar trigate Tunnel FET (TFET) for dynamic memory applications. Results demonstrate the significance of electric field (EF) at each junction i.e. Source-Gate1 (S-G1), Drain-Gate2 (D-G2), and that between gates, evaluated through the energy barrier between G1-G2 (Eb) to improve Sense Margin (SM), Current Ratio (CR), speed (write time) and Retention Time (RT). The work highlights the impact of device parameters that aid to improve the performance metrics, and also reduce the associated trade-offs in dynamic memory.
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