{"title":"A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application","authors":"Keishi Tsubaki, T. Hirose, N. Kuroki, M. Numa","doi":"10.1109/ESSCIRC.2013.6649136","DOIUrl":null,"url":null,"abstract":"This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz. The power dissipation was 472 nW. Measured line regulation and temperature coefficient were 1.1%/V and 120ppm/°C, respectively.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"38","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2013.6649136","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 38
Abstract
This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz. The power dissipation was 472 nW. Measured line regulation and temperature coefficient were 1.1%/V and 120ppm/°C, respectively.