J. Lee, Heung-Soo Im, D. Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyongjoo Lee, Y. Lim, Jungdal Choi, Young-Il Seo, Jong-Sik Lee, K. Suh
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引用次数: 3
Abstract
A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.
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