An 8b monolithic ADC

Abstract

THIS PAPER will report on a monolithic 8 b flash A / D converter which digitizes more than 40MIk signal at 120MS/s and requires no external sample-and-hold circuit. The ADC I S 1 contains 256 comparators, encoder logics, data latches for pip(: line Operation, clock drivers and output buffers. Although the flash ADC offers the possibility of fast conversion and no requirement of samplc-and-hold circuit. it is also necessarv to cmploy many comparators which consume power. Therefore, a high-speed and low-power comparator must be implemented to achieve an ultrahigh speed ADC which has a conversion rate in excess o f 10OVl1-Iz. Figure 1 shows the comparator circuit of the .4DC ISI . The comparator consists of three stages; the first stage is a differential amplifier, the second is a master-latch which samples the analog input signal; and the third is a slave-latch. The differential amplifier is included to prevent talk back of the clock pulse from thc latch circuit to the analog input port. Besides, the amplifier is provided to increase the amplitude of the input signal to the master-latch stage, hence these results improve the latch speed. At the input port, leakage current of 0.4p.4 is detected by the talk back. How-ever, this valuc is one twenty-fifth of the talk back of the conventional comparator’. The master-and-slave latches arc implemented to improve the clock rate. A n AND gate arranged at the output of the master-latch stage examines the outputs of own comparator and two adjacent comparators. The differential amplifier provides a gain of 6. Both latches of the master and slave acquire the signal in only Ins when the overdrive voltage is LmV. Only 1.5ns is needed to recover from the latched state. The current consumption per one comparator is 1.2mA with the voltage bource (VEE) of -5.2V. Encoder circuitry requires large power consumption to maintain ultrahigh speed, since this is composed of a transistor matrix and hence requires large fan-in and fan-out. To solve this problem, a switching current source is employed in the cucoder circuitry to reduce the power consumption while maintaining hgh speed operation. Figure 2 shows a simplified schematic of the encoder circuitry. Since the output signal from only one comparator is at the high level, only the diode, which is connected to the emitter-follower of that comparator, is activated to ON state. Diodes connected to the other comparators remain at OFF state. Therefore, the charge accumulated at bases o f the encoder matrix is swept away via the ON diode with constant current. One constant current sourcc of 40OpA is implemented per sixteen comparators, and an output emitter-follower of each comparator is opcrated with sink-current of 30pA. Accordingly, the current consumption of the output emitter-followcr of the comparators has bemable to at tain a 86% reduction, compared with the encodcr circuitry, which docs not have such a switching current sourcc. In an ultrahigh speed flash ADC; it is extremtly difficult to convert Gray code into pure-binary code, since sub-nanosecond exclusive-OR gates arc required. Therefore, it is necessary t o irnplemcnt thc encoder logics which must convert analog signal into pure-binary code directly, without missing code. The missing code tends to appear at the transitions of the MSBs which correspond to the folding points of the comparator layout. To solve this problem, an inhibit circuit has been inserted between two adjacent comparator groups, as shown in Figurc 3. Each comparator group consists of thirty-two comparators whose output signals arc converted into lower 5b binary codc. Then an OR gate (e.g., OR2A) is provided to examine thc latch outputs of the 5LSB bits signals. The output of the OR gate inhibits the 5133 bits of next comparator group, if any one of the 51,SB bits signals are at a high level. The process used is a self-aligned 2pm bipolar technology. Essential to the fabrication are an ion-implantation of base and emitter, and a BSG diffusion of an inactive base for good base-emitter voltage matching. The size of the emitter contact is just the same as the emitter area. Thickness of the epitaxial layer is 2pm and the base width is typically 0.2pm. Thc f~ value at the emitter current of 200pA, which is equal to the sink-current o f the comparator, is 2.5GHz. The distribution of the base-emitter offscts of 4 x 4pm emitter size transistor pairs is 0.2mV as the starrdard deviation; 3 0. Figure 4 shows a reconstructed 4OMHz sine wave after sampling at a 12OMI-Iz conversion rate. Figure 5 is the result of beat-frequency tcst under the conversion frequency of 12OMHz and input frequency of 30.1MHz; hence beat frcquency is 0.1MIlz. When the input signal to this converter is 3031Hz, the S/N ratio is 40dB. A list of major characteristics is shown in Table 1. Figure 6 is a photograph of the ADC IS1 which contains 24,000 components. Chip size is 4.3mm x 7.5mm.