Power distribution for highly parallel WSI architectures

Abstract

An investigation of the transient noise-coupled currents and their effect on voltage integrity is discussed. The investigation has been undertaken using an extracted-load simulation technique with a typical fine-grain systolic array-based architectures as the research vehicle. Simulation results indicate that potentially harmful power supply resonances of up to 40-ns duration can occur. Although these can be brought under control with peripheral decoupling components, serious problems associated with the maintenance of acceptable voltage integrity, with standard power distribution technology can occur when the device size is increased beyond 35-mm on a side. Although such sizes are significantly larger than current VLSI, they are clearly at least a factor or two less than monolithic WSI, thus suggesting that an alternative power distribution technology must be sought.<>