Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47545
F. Blayo, P. Hurat
The solution presented consists of implementing the N neuron Hopfield network as a systolic square array made up of N/sup 2/ cells. Systolic arrays are well suited to wafer-scale integration (WSI). Inherent error tolerance of neural networks facilitates wafer design. However, a wafer-level reconfiguration is required to bypass faulty chips. The principle and the architecture of a switching element which provides a flexible wafer-level reconfiguration is described.<>
{"title":"A reconfigurable WSI neural network","authors":"F. Blayo, P. Hurat","doi":"10.1109/WAFER.1989.47545","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47545","url":null,"abstract":"The solution presented consists of implementing the N neuron Hopfield network as a systolic square array made up of N/sup 2/ cells. Systolic arrays are well suited to wafer-scale integration (WSI). Inherent error tolerance of neural networks facilitates wafer design. However, a wafer-level reconfiguration is required to bypass faulty chips. The principle and the architecture of a switching element which provides a flexible wafer-level reconfiguration is described.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"52 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126005539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47537
J. Kallis, L. B. Duncan, S. Laub, M. J. Little, L.M. Miani, D.C. Sandkulla
An assessment of the mechanical reliability of the 3-D Computer is presented. The purpose of this reliability assessment was to gain confidence in the feasibility of this stacked-wafer approach for space-based applications. The investigation addressed both the mechanical and thermal reliability by means of analyses and experiments.<>
{"title":"Reliability of the 3-D computer under stress of mechanical vibration and thermal cycling","authors":"J. Kallis, L. B. Duncan, S. Laub, M. J. Little, L.M. Miani, D.C. Sandkulla","doi":"10.1109/WAFER.1989.47537","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47537","url":null,"abstract":"An assessment of the mechanical reliability of the 3-D Computer is presented. The purpose of this reliability assessment was to gain confidence in the feasibility of this stacked-wafer approach for space-based applications. The investigation addressed both the mechanical and thermal reliability by means of analyses and experiments.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129568403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47535
B. Warren, W. Richardson, K. Kanegawa, C. Arnell, H. Shimizu, K. Nakai, S. Hara, K. Ichiba
A monolithic 1-Mb static random-access memory (SRAM) with a typical access time of 55 ns, fabricated using 1.2- mu m CMOS technology, is described. The product incorporates a design approach that permits the manufacture of next-generation products (0.8- mu m 1-Mb SRAMs) on current, well-understood production processes. The yield history using this technique supports wafer-level repetitive structures such as memory, or processor/memory combinations. Supporting actual yield data are presented. The product is constructed of many small memories that are fabricated through metal 1, then tested and laser repaired and subsequently interconnected, using a nondiscretionary metal 2 layer, into a much larger memory system.<>
介绍了一种采用1.2 μ m CMOS技术制作的单片1mb静态随机存取存储器(SRAM)，典型存取时间为55ns。该产品采用了一种设计方法，允许在当前的、众所周知的生产工艺上制造下一代产品(0.8 μ m 1mb sram)。使用该技术的良率历史支持晶圆级重复结构，如内存或处理器/内存组合。给出了支持实际产量的数据。该产品由许多小型存储器组成，这些存储器通过金属制造，然后测试和激光修复，随后使用非任意金属层连接成一个更大的存储系统。
{"title":"A one megabit SRAM fabricated with 1.2 mu technology","authors":"B. Warren, W. Richardson, K. Kanegawa, C. Arnell, H. Shimizu, K. Nakai, S. Hara, K. Ichiba","doi":"10.1109/WAFER.1989.47535","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47535","url":null,"abstract":"A monolithic 1-Mb static random-access memory (SRAM) with a typical access time of 55 ns, fabricated using 1.2- mu m CMOS technology, is described. The product incorporates a design approach that permits the manufacture of next-generation products (0.8- mu m 1-Mb SRAMs) on current, well-understood production processes. The yield history using this technique supports wafer-level repetitive structures such as memory, or processor/memory combinations. Supporting actual yield data are presented. The product is constructed of many small memories that are fabricated through metal 1, then tested and laser repaired and subsequently interconnected, using a nondiscretionary metal 2 layer, into a much larger memory system.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123592774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47559
J.J. Shen, I. Koren
Yield enhancement designs for wafer-scale cube-connected cycles (CCCs) are presented and analyzed. Improvements in yield can be achieved through silicon area reduction and/or through the incorporation of defect/fault tolerance in the architecture. Consequently, a compact layout strategy is proposed for CCCs. An implementation of wafer-scale CCCs based on a universal building block is presented. This implementation facilitates the introduction of redundancy to achieve direct-tolerance. Expressions for the yield of various yield enhancement designs are derived and compared numerically for several sizes of wafer-scale CCCs.<>
{"title":"Yield enhancement designs for WSI cube connected cycles","authors":"J.J. Shen, I. Koren","doi":"10.1109/WAFER.1989.47559","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47559","url":null,"abstract":"Yield enhancement designs for wafer-scale cube-connected cycles (CCCs) are presented and analyzed. Improvements in yield can be achieved through silicon area reduction and/or through the incorporation of defect/fault tolerance in the architecture. Consequently, a compact layout strategy is proposed for CCCs. An implementation of wafer-scale CCCs based on a universal building block is presented. This implementation facilitates the introduction of redundancy to achieve direct-tolerance. Expressions for the yield of various yield enhancement designs are derived and compared numerically for several sizes of wafer-scale CCCs.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130707699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47553
V.K.P. Kumar, Yi-Chen Tsai
A general methodology to map computations carried out on two-dimensional systolic arrays onto one-dimensional arrays is developed. The basic idea of the technique is to map computations of two-dimensional systolic arrays onto one-dimensional arrays in such a way that they satisfy the dependencies in the original problem. Using the technique, the two-dimensional arrays that have been developed for a large class of problems can be translated into one-dimensional arrays with the designs which can be implemented in wafer-scale integration (WSI). Compared to known designs in the literature, the methodology is an improvement in that it leads to modular systolic arrays with contrast hardware in each processing element, few control lines, lexicographic data input/output format, and improved delay time.<>
{"title":"Mapping algorithms to linear systolic arrays for wafer scale integration","authors":"V.K.P. Kumar, Yi-Chen Tsai","doi":"10.1109/WAFER.1989.47553","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47553","url":null,"abstract":"A general methodology to map computations carried out on two-dimensional systolic arrays onto one-dimensional arrays is developed. The basic idea of the technique is to map computations of two-dimensional systolic arrays onto one-dimensional arrays in such a way that they satisfy the dependencies in the original problem. Using the technique, the two-dimensional arrays that have been developed for a large class of problems can be translated into one-dimensional arrays with the designs which can be implemented in wafer-scale integration (WSI). Compared to known designs in the literature, the methodology is an improvement in that it leads to modular systolic arrays with contrast hardware in each processing element, few control lines, lexicographic data input/output format, and improved delay time.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130725598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47540
R. Westmore
A wafer-scale architecture for the real-time generation of shaded, full-color perspective images of complex three-dimensional scenes is described, The system is capable of operating at the high pixel rates required to produce scenes in real time on high-resolution screens with high refresh rates. This image generation architecture meets the requirements of Catt's fault tolerant approach to wafer-scale integration circuits.<>
{"title":"A scaleable waferscale architecture for real-time 3-D image generation","authors":"R. Westmore","doi":"10.1109/WAFER.1989.47540","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47540","url":null,"abstract":"A wafer-scale architecture for the real-time generation of shaded, full-color perspective images of complex three-dimensional scenes is described, The system is capable of operating at the high pixel rates required to produce scenes in real time on high-resolution screens with high refresh rates. This image generation architecture meets the requirements of Catt's fault tolerant approach to wafer-scale integration circuits.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133208382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47561
U. Ramacher, J. Beichter, W. Kamp
The design of a 6.8*6-cm wafer-scale integration (WSI) chip for matrix-matrix multiplication, the layout, and its verification hierarchy are described. The chip is designed in a defect-tolerant style. Whole wafer lithography resulting in 2- mu m effective design rules was chosen because of reduced costs of masks.<>
{"title":"On the design of a selftesting WSI multiplier array","authors":"U. Ramacher, J. Beichter, W. Kamp","doi":"10.1109/WAFER.1989.47561","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47561","url":null,"abstract":"The design of a 6.8*6-cm wafer-scale integration (WSI) chip for matrix-matrix multiplication, the layout, and its verification hierarchy are described. The chip is designed in a defect-tolerant style. Whole wafer lithography resulting in 2- mu m effective design rules was chosen because of reduced costs of masks.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"370 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115194381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47555
A. Stewart
A fault-tolerant ultra large-scale integration (ULSI) signal processor which handles 32-bit floating-point data conforming to IEEE standard 754 and includes sufficient on-chip random access memory to perform a 1024-point fast Fourier transform (FFT) without reference to external memory is discussed. The chip is designed to run at 32 MHz using completely standard 1.5- mu m bulk CMOS technology, with an estimated chip size of 4 cm/sup 2/. In FFT mode, one FFT butterfly operation can be started every clock cycle such that a complete 1024-point complex FFT is completed in 160- mu s (typ). The aim is to raise the yield of the device to the point where a multiprocessor system can be realized from a small array of these processors.<>
讨论了一种容错超大规模集成(ULSI)信号处理器，该处理器处理符合IEEE 754标准的32位浮点数据，并具有足够的片上随机存取存储器，可在不参考外部存储器的情况下执行1024点快速傅立叶变换(FFT)。该芯片采用完全标准的1.5 μ m大块CMOS技术，设计运行在32 MHz，估计芯片尺寸为4 cm/sup /。在FFT模式下，每个时钟周期可以启动一个FFT蝴蝶运算，从而在160 μ s (type)内完成一个完整的1024点复杂FFT。其目的是提高器件的成品率，使多处理器系统可以从这些处理器的小阵列中实现
{"title":"The development of a fault tolerant ULSI signal processor","authors":"A. Stewart","doi":"10.1109/WAFER.1989.47555","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47555","url":null,"abstract":"A fault-tolerant ultra large-scale integration (ULSI) signal processor which handles 32-bit floating-point data conforming to IEEE standard 754 and includes sufficient on-chip random access memory to perform a 1024-point fast Fourier transform (FFT) without reference to external memory is discussed. The chip is designed to run at 32 MHz using completely standard 1.5- mu m bulk CMOS technology, with an estimated chip size of 4 cm/sup 2/. In FFT mode, one FFT butterfly operation can be started every clock cycle such that a complete 1024-point complex FFT is completed in 160- mu s (typ). The aim is to raise the yield of the device to the point where a multiprocessor system can be realized from a small array of these processors.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114543889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47538
M. Yung, M. Little, R. D. Etchells, J. G. Nash
A prototype 3-D Computer which demonstrates the feasibility of the stacked wafer approach is discussed. The wafer-scale integrated circuits of the 3-D Computer have been carefully partitioned to enable redundancy to be used to insure high yields. Redundancy approaches, implementation issues, and testability both for the schemes used in the prototype and in future generations of the 3-D Computer are discussed. The circuits of the 32*32 array processor used 100% interstitial redundancy using one-way connectivity. The 128*128 array processor now underway construction, as well as a future larger array processor, use a mixture of redundancy schemes: a 50% redundancy with four-way connectivity for the array logic and 100% redundancy for the nearest-neighbor communication and control circuits. The 50% redundancy minimizes the area and test overhead for sparing while improving yields.<>
{"title":"Redundancy for yield enhancement in the 3-D computer","authors":"M. Yung, M. Little, R. D. Etchells, J. G. Nash","doi":"10.1109/WAFER.1989.47538","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47538","url":null,"abstract":"A prototype 3-D Computer which demonstrates the feasibility of the stacked wafer approach is discussed. The wafer-scale integrated circuits of the 3-D Computer have been carefully partitioned to enable redundancy to be used to insure high yields. Redundancy approaches, implementation issues, and testability both for the schemes used in the prototype and in future generations of the 3-D Computer are discussed. The circuits of the 32*32 array processor used 100% interstitial redundancy using one-way connectivity. The 128*128 array processor now underway construction, as well as a future larger array processor, use a mixture of redundancy schemes: a 50% redundancy with four-way connectivity for the array logic and 100% redundancy for the nearest-neighbor communication and control circuits. The 50% redundancy minimizes the area and test overhead for sparing while improving yields.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121686493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/WAFER.1989.47566
J. Guilford, E. H. Rogers
The design of the internal node for the WaRP wafer-scale database machine is described. The WaRP architecture consists of a binary tree laid out on a wafer. Most of the data storage and processing occurs in the leaf nodes. The internal nodes of the tree are given the task of distributing queries to the leaves and combining responses. The tree is both fault tolerant and soft-prunable in the field; it is possible to both test the tree and to prune away faulty nodes. As a result, most of the internal node is concerned with testability.<>
{"title":"A self-testing and self-pruning binary communication tree for a wafer scale database system","authors":"J. Guilford, E. H. Rogers","doi":"10.1109/WAFER.1989.47566","DOIUrl":"https://doi.org/10.1109/WAFER.1989.47566","url":null,"abstract":"The design of the internal node for the WaRP wafer-scale database machine is described. The WaRP architecture consists of a binary tree laid out on a wafer. Most of the data storage and processing occurs in the leaf nodes. The internal nodes of the tree are given the task of distributing queries to the leaves and combining responses. The tree is both fault tolerant and soft-prunable in the field; it is possible to both test the tree and to prune away faulty nodes. As a result, most of the internal node is concerned with testability.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133242965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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