Electrical modeling of an IC package chip paddle as an integral ground bus

Abstract

This paper presents an analysis of an IC package chip paddle connected as an active ground bus to conduct ground currents from the chip to the system ground. To generate the electrical models, non-commercial software acquired through various university sources was utilized. The development of associated software to provide efficient input of CAD data base information and output to simulation programs is briefly described. Various paddle designs and the number and placement of ground path bond wires are modeled and simulated and the results presented.