Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606149
E. Takano, T. Mino, K. Takahashi, K. Sawada, S. Shimizu, H. Yoo
Copper alloy leadframe has good thermal, electrical, mechanical and cost performance. It, however, is susceptible to package cracking during reflow soldering due to poor adhesion of the molding compound to the leadframe. In this paper we investigated the oxide film properties of copper leadframe and the effect of the film on the reliability performance of semiconductor packages. According to our experiment, oxide film growth was expressed as a function of time and temperature and the growth of the oxide film was surpressed when oxygen concentration was less than 5%. An adhesion strength test of epoxy molding compound to the oxidized copper surface showed drastic degradation of strength if the film thickness exceeded about 20 nm accompanied with delaminating surface alternation. Finally, we conducted a reflow cracking test with samples whose oxide film thickness was controlled. The results showed good correlation with the adhesion strength test. It was found that the oxide film thickness should be less than 40 nm to enhance reflow crack performance.
{"title":"The oxidation control of copper leadframe package for prevention of popcorn cracking","authors":"E. Takano, T. Mino, K. Takahashi, K. Sawada, S. Shimizu, H. Yoo","doi":"10.1109/ECTC.1997.606149","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606149","url":null,"abstract":"Copper alloy leadframe has good thermal, electrical, mechanical and cost performance. It, however, is susceptible to package cracking during reflow soldering due to poor adhesion of the molding compound to the leadframe. In this paper we investigated the oxide film properties of copper leadframe and the effect of the film on the reliability performance of semiconductor packages. According to our experiment, oxide film growth was expressed as a function of time and temperature and the growth of the oxide film was surpressed when oxygen concentration was less than 5%. An adhesion strength test of epoxy molding compound to the oxidized copper surface showed drastic degradation of strength if the film thickness exceeded about 20 nm accompanied with delaminating surface alternation. Finally, we conducted a reflow cracking test with samples whose oxide film thickness was controlled. The results showed good correlation with the adhesion strength test. It was found that the oxide film thickness should be less than 40 nm to enhance reflow crack performance.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122934353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606313
Q. Tan, Wenge Zhang, B. Schaible, L. Bond, T. Ju, Y.C. Lee
Flip-chip assembly is an important technology for first level electronic packaging. Among different assembly approaches, thermosonic bonding is becoming an attractive choice because it is cost-effective. To increase the bonding capability for high I/O assembly, a novel longitudinal bonding system is developed in this study. This bonding system has two advantages over the transverse bonding system: it overcomes the planarity problem and simplifies bonding tool configuration. During the development, an end-effector is designed with rigorous considerations of ultrasonic wave propagation, bonding force and co-planarity between the chip holder and hot stage. The bonding system is then characterized to make sure that it is suitable for flip-chip assembly. This bonding technology is proven successful by mechanical bonding tests as well as a functional CMOS/SRAM module demonstration. During the bonding process, the chip is under longitudinal ultrasonic "hammering". However, there is no apparent damage because the impact stress is low due to the low ultrasonic vibration amplitude.
{"title":"Thermosonic flip-chip bonding using longitudinal ultrasonic vibration","authors":"Q. Tan, Wenge Zhang, B. Schaible, L. Bond, T. Ju, Y.C. Lee","doi":"10.1109/ECTC.1997.606313","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606313","url":null,"abstract":"Flip-chip assembly is an important technology for first level electronic packaging. Among different assembly approaches, thermosonic bonding is becoming an attractive choice because it is cost-effective. To increase the bonding capability for high I/O assembly, a novel longitudinal bonding system is developed in this study. This bonding system has two advantages over the transverse bonding system: it overcomes the planarity problem and simplifies bonding tool configuration. During the development, an end-effector is designed with rigorous considerations of ultrasonic wave propagation, bonding force and co-planarity between the chip holder and hot stage. The bonding system is then characterized to make sure that it is suitable for flip-chip assembly. This bonding technology is proven successful by mechanical bonding tests as well as a functional CMOS/SRAM module demonstration. During the bonding process, the chip is under longitudinal ultrasonic \"hammering\". However, there is no apparent damage because the impact stress is low due to the low ultrasonic vibration amplitude.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122582437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606228
Y. Joshi, A. Bar-Cohen, S. Bhavnani
Electronics packaging education requires a multidisciplinary approach, integrating concepts in electrical engineering, materials, structural analysis, heat transfer, reliability and computational methods. The availability of advanced instructional technologies is allowing an unprecedented opportunity to incorporate several desirable attributes to courseware development in such areas. This paper describes an ongoing multi-university effort undertaken to develop a national course on thermal design of electronic products. The participating institutions provide a combination of faculty with expertise in various aspects of thermal design. Examples of course materials developed so far include: (i) videotaped lecture segments on specialized topics, (ii) case studies, and (iii) multi-media computational design simulations. At each institution, the modules are integrated with traditional classroom lectures. These materials will form a central online resource base, accessible through the world wide web (WWW). In addition to their possible use in courses dealing specifically with electronics cooling, it is anticipated that instructors of more comprehensive packaging courses, as well as more general heat transfer and thermal design courses, will find it possible to incorporate these modules in their syllabi and thus dramatically expand the number of engineering students exposed to these critical issues.
{"title":"Distance learning paradigms in electronics packaging: a national course on thermal design of electronic products","authors":"Y. Joshi, A. Bar-Cohen, S. Bhavnani","doi":"10.1109/ECTC.1997.606228","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606228","url":null,"abstract":"Electronics packaging education requires a multidisciplinary approach, integrating concepts in electrical engineering, materials, structural analysis, heat transfer, reliability and computational methods. The availability of advanced instructional technologies is allowing an unprecedented opportunity to incorporate several desirable attributes to courseware development in such areas. This paper describes an ongoing multi-university effort undertaken to develop a national course on thermal design of electronic products. The participating institutions provide a combination of faculty with expertise in various aspects of thermal design. Examples of course materials developed so far include: (i) videotaped lecture segments on specialized topics, (ii) case studies, and (iii) multi-media computational design simulations. At each institution, the modules are integrated with traditional classroom lectures. These materials will form a central online resource base, accessible through the world wide web (WWW). In addition to their possible use in courses dealing specifically with electronics cooling, it is anticipated that instructors of more comprehensive packaging courses, as well as more general heat transfer and thermal design courses, will find it possible to incorporate these modules in their syllabi and thus dramatically expand the number of engineering students exposed to these critical issues.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114147721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606173
A. Miura, K. Tonehira, A. Takai, S. Aoki, S. Kaneko, H. Irie, S. Hanatani
We developed 200-Mbit/s/ch, 12-ch, 100-m, +3.3 V CMOS interface, fully integrated optical interconnects using single-mode fiber arrays, planar micro-lens arrays and 1.6-mA-threshold-current 1.3 /spl mu/m laser diode (LD) arrays. Skew and BER measurement and reliability test result confirmed the reliable optical interconnects for communication and computer systems in practical use.
{"title":"Reliable, compact, CMOS interface, 200-Mbit/s a 12-channel optical interconnects using single-mode fiber arrays","authors":"A. Miura, K. Tonehira, A. Takai, S. Aoki, S. Kaneko, H. Irie, S. Hanatani","doi":"10.1109/ECTC.1997.606173","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606173","url":null,"abstract":"We developed 200-Mbit/s/ch, 12-ch, 100-m, +3.3 V CMOS interface, fully integrated optical interconnects using single-mode fiber arrays, planar micro-lens arrays and 1.6-mA-threshold-current 1.3 /spl mu/m laser diode (LD) arrays. Skew and BER measurement and reliability test result confirmed the reliable optical interconnects for communication and computer systems in practical use.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114506219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606266
M. Lamson
This paper presents an analysis of an IC package chip paddle connected as an active ground bus to conduct ground currents from the chip to the system ground. To generate the electrical models, non-commercial software acquired through various university sources was utilized. The development of associated software to provide efficient input of CAD data base information and output to simulation programs is briefly described. Various paddle designs and the number and placement of ground path bond wires are modeled and simulated and the results presented.
{"title":"Electrical modeling of an IC package chip paddle as an integral ground bus","authors":"M. Lamson","doi":"10.1109/ECTC.1997.606266","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606266","url":null,"abstract":"This paper presents an analysis of an IC package chip paddle connected as an active ground bus to conduct ground currents from the chip to the system ground. To generate the electrical models, non-commercial software acquired through various university sources was utilized. The development of associated software to provide efficient input of CAD data base information and output to simulation programs is briefly described. Various paddle designs and the number and placement of ground path bond wires are modeled and simulated and the results presented.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117265528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606242
T. Ogashiwa, T. Arikawa, A. Inoue
A direct soldering material with Al thin-film pad has been examined for a bare flip-chip bonding on Printed Wiring Board. A solder ball made from the. 59.6Sn-29Pb-5Sb-1Zn-5Ag-0.2Cu-0.2Ni (mass%) alloy wire was thermosonically bonded on the Al-1%Si pad by using a conventional bump bonding machine. For fine-pitch bonding, the strain of ball deformation can be reduced by finding the optimum value of the ultrasonic power for bond strength and ellipticity of the bonded bump. After reflow treatment up to 300/spl deg/C, no significant degradation of the bump shear force was observed. The concentration of Ag, Cu and Ni in the Al film interface results in an improvement in heat-resistance at the bond interface against the high reflow temperatures. Furthermore, the consistency of measured resistance values during thermal cycling, high-temperature and high-humidity and pressure cooker tests were sufficient enough to put into practical use in epoxy encapsulated flip-chip assemblies.
{"title":"Development of reflowable Sn-Pb alloy bump for Al pad","authors":"T. Ogashiwa, T. Arikawa, A. Inoue","doi":"10.1109/ECTC.1997.606242","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606242","url":null,"abstract":"A direct soldering material with Al thin-film pad has been examined for a bare flip-chip bonding on Printed Wiring Board. A solder ball made from the. 59.6Sn-29Pb-5Sb-1Zn-5Ag-0.2Cu-0.2Ni (mass%) alloy wire was thermosonically bonded on the Al-1%Si pad by using a conventional bump bonding machine. For fine-pitch bonding, the strain of ball deformation can be reduced by finding the optimum value of the ultrasonic power for bond strength and ellipticity of the bonded bump. After reflow treatment up to 300/spl deg/C, no significant degradation of the bump shear force was observed. The concentration of Ag, Cu and Ni in the Al film interface results in an improvement in heat-resistance at the bond interface against the high reflow temperatures. Furthermore, the consistency of measured resistance values during thermal cycling, high-temperature and high-humidity and pressure cooker tests were sufficient enough to put into practical use in epoxy encapsulated flip-chip assemblies.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123936741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606209
B. Schaible, Y.C. Lee, H. Xie
With ever decreasing design cycles, it is important for designers to have techniques they can use to quickly and efficiently model new designs. From these models, package performance can be estimated and electrical, thermal, and mechanical considerations can be balanced. In this paper, we present a method of quickly investigating new design concepts based on knowledge of previously studied designs and knowledge of the differences between the new and old designs. This approach is useful when the difference between designs is simple and can be accurately modeled with fewer data. The use of less data equates to a savings of time and money. In the case studies presented, we establish two "base" models using 40 data each, then we establish two additional models of similar processes using only five and seven data each. Here, the initial (base) design and the design differences are modeled with fuzzy logic based regression models. Such fuzzy logic regression models can be based on numerically or empirically obtained data or physical knowledge of the system to be modeled. Once established, these models have the advantage of offering very fast response times uncharacteristic of experimentation, prototyping, and numerical methods such as finite element, finite difference, or boundary element modeling.
{"title":"Efficient design using fuzzy logic based regression models","authors":"B. Schaible, Y.C. Lee, H. Xie","doi":"10.1109/ECTC.1997.606209","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606209","url":null,"abstract":"With ever decreasing design cycles, it is important for designers to have techniques they can use to quickly and efficiently model new designs. From these models, package performance can be estimated and electrical, thermal, and mechanical considerations can be balanced. In this paper, we present a method of quickly investigating new design concepts based on knowledge of previously studied designs and knowledge of the differences between the new and old designs. This approach is useful when the difference between designs is simple and can be accurately modeled with fewer data. The use of less data equates to a savings of time and money. In the case studies presented, we establish two \"base\" models using 40 data each, then we establish two additional models of similar processes using only five and seven data each. Here, the initial (base) design and the design differences are modeled with fuzzy logic based regression models. Such fuzzy logic regression models can be based on numerically or empirically obtained data or physical knowledge of the system to be modeled. Once established, these models have the advantage of offering very fast response times uncharacteristic of experimentation, prototyping, and numerical methods such as finite element, finite difference, or boundary element modeling.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116467206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606245
R. Kaw, B. Hanna, N. Devnani
The exclusive domain of modeling and design for CPU packaging is beginning to find its way into the ASIC world as well. As the feature sizes decrease from 0.5 to 0.35 to 0.25 micron, the drivers become faster with sub-nsec transitions. Most of these ASICs service the ever widening word width, that has changed from 32 to 64 bits, and on to the wide word. Thus, in general, we have a gradual shift towards pad-limited designs that demand an ever-decreasing pitch, with very fast drivers switching simultaneously in large numbers. An increasing number of these ASICs dissipate more than the capability of ordinary plastic packages. This is a crowded, hot, and noisy environment that can be managed only by concurrent design of chip padout and package layout from an electrical perspective, and the system board/box design from a thermo-mechanical perspective. At the very least, it demands package selection based on electrical modeling of noise, generated by the chip and its package. This paper presents a study of three package styles for an ASIC with 270 signals. The design space for this chip type is expected to handle heat dissipation of 2 to 15 watts. That rules out most ordinary plastic packages, unless they are thermally enhanced. The packages selected for comparison, in this study, are of the enhanced BGA type. All of them use a heat spreader to which the chip is attached for thermal management. The study consists of: (a) an evaluation of how best to design the chip padout concurrently with the possibilities offered by the layout rules of these packages; (b) electrical models of these designs are used to calculate the various kinds of noise for each package type. The results are summarized for easy comparison, along with the assumptions made, to enable reasonable projections from these results.
{"title":"Comparison of electrical performance of enhanced BGAs","authors":"R. Kaw, B. Hanna, N. Devnani","doi":"10.1109/ECTC.1997.606245","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606245","url":null,"abstract":"The exclusive domain of modeling and design for CPU packaging is beginning to find its way into the ASIC world as well. As the feature sizes decrease from 0.5 to 0.35 to 0.25 micron, the drivers become faster with sub-nsec transitions. Most of these ASICs service the ever widening word width, that has changed from 32 to 64 bits, and on to the wide word. Thus, in general, we have a gradual shift towards pad-limited designs that demand an ever-decreasing pitch, with very fast drivers switching simultaneously in large numbers. An increasing number of these ASICs dissipate more than the capability of ordinary plastic packages. This is a crowded, hot, and noisy environment that can be managed only by concurrent design of chip padout and package layout from an electrical perspective, and the system board/box design from a thermo-mechanical perspective. At the very least, it demands package selection based on electrical modeling of noise, generated by the chip and its package. This paper presents a study of three package styles for an ASIC with 270 signals. The design space for this chip type is expected to handle heat dissipation of 2 to 15 watts. That rules out most ordinary plastic packages, unless they are thermally enhanced. The packages selected for comparison, in this study, are of the enhanced BGA type. All of them use a heat spreader to which the chip is attached for thermal management. The study consists of: (a) an evaluation of how best to design the chip padout concurrently with the possibilities offered by the layout rules of these packages; (b) electrical models of these designs are used to calculate the various kinds of noise for each package type. The results are summarized for easy comparison, along with the assumptions made, to enable reasonable projections from these results.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124074469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606338
N. Hwang, S. Kang, H. Lee, Seong-Su Park, Min-Kyu Song, K. Pyun
An empirical method for lifetime projection of 1.55 /spl mu/m InGaAs/InP MQW-DFB laser diodes (LD) is presented. On the basis of experimental results of accelerated aging test for 1500 hours, relationship between LD degradation, operating voltage, and ambient temperature has been determined. The presented method makes it possible to predict the lifetime of LDs by determining the thermal voltage ratio.
提出了1.55 /spl μ m InGaAs/InP MQW-DFB激光二极管(LD)寿命投影的经验方法。在1500小时加速老化试验的基础上，确定了LD降解与工作电压、环境温度之间的关系。该方法可以通过确定热电压比来预测lcd的寿命。
{"title":"An empirical reliability prediction method for 1.55 /spl mu/m InGaAs/InP MQW-DFB laser diodes","authors":"N. Hwang, S. Kang, H. Lee, Seong-Su Park, Min-Kyu Song, K. Pyun","doi":"10.1109/ECTC.1997.606338","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606338","url":null,"abstract":"An empirical method for lifetime projection of 1.55 /spl mu/m InGaAs/InP MQW-DFB laser diodes (LD) is presented. On the basis of experimental results of accelerated aging test for 1500 hours, relationship between LD degradation, operating voltage, and ambient temperature has been determined. The presented method makes it possible to predict the lifetime of LDs by determining the thermal voltage ratio.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132367416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606226
G. S. May
In response to the changing ethnicity of the U.S. work force and the dearth of individuals from under-represented groups pursuing careers in technical fields, the Georgia Tech Summer Undergraduate Packaging Research and Engineering Experience for Minorities (GT-SUPREEM) has been developed to attract qualified minority students to pursue graduate degrees in electronics packaging-related disciplines. The program is conducted under the auspices of the Georgia Tech Engineering Research Center in Low-Cost Electronic Packaging, which is sponsored by the National Science Foundation. In the GT-SUPREEM program, junior and senior level undergraduate students are selected on a nationwide basis and paired with a faculty advisor to undertake research projects in the Packaging Research Center. The students are housed on campus and provided with a $3,000 stipend and a travel allowance. At the conclusion of the program, the students present both oral and written project summaries. It has been shown that this experience is extremely successful in motivating these students to attend graduate school, with 89% of the participants opting to do so. This paper will provide an overview of the GT-SUPREEM program, including student research activities, success stories, lessons learned, and overall program outlook.
{"title":"Educating under-represented minority students in electronics packaging for the 21st century","authors":"G. S. May","doi":"10.1109/ECTC.1997.606226","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606226","url":null,"abstract":"In response to the changing ethnicity of the U.S. work force and the dearth of individuals from under-represented groups pursuing careers in technical fields, the Georgia Tech Summer Undergraduate Packaging Research and Engineering Experience for Minorities (GT-SUPREEM) has been developed to attract qualified minority students to pursue graduate degrees in electronics packaging-related disciplines. The program is conducted under the auspices of the Georgia Tech Engineering Research Center in Low-Cost Electronic Packaging, which is sponsored by the National Science Foundation. In the GT-SUPREEM program, junior and senior level undergraduate students are selected on a nationwide basis and paired with a faculty advisor to undertake research projects in the Packaging Research Center. The students are housed on campus and provided with a $3,000 stipend and a travel allowance. At the conclusion of the program, the students present both oral and written project summaries. It has been shown that this experience is extremely successful in motivating these students to attend graduate school, with 89% of the participants opting to do so. This paper will provide an overview of the GT-SUPREEM program, including student research activities, success stories, lessons learned, and overall program outlook.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131143825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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