Six subthreshold full adder cells characterized in 90 nm CMOS technology

Abstract

This paper presents a performance analysis and evaluation of six different 1-bit full adder topologies in deep subthreshold operation. The cells are characterized with respect to delay, power consumption, driving capability, power-delay product (PDP), energy-delay product (EDP) and maximum operating frequency. Both traditional CMOS, a specialized low power cell and minority-3 based full adders are simulated and characterized. PDPs of less than 200 aJ are reported, for FA cells operating at frequencies around 2 MHz, for Vdd=200 mV, dissipating less than 100 nW of average power