Compilation-based software performance estimation for system level design

Abstract

The paper addresses embedded software performance estimation. Known approaches use either behavioral simulation with timing annotations, or a clock cycle-accurate model of instruction execution (e.g., an instruction set simulator). We propose a hybrid approach, that features both the high simulation speed and flexibility from the former approach and the awareness of compilation optimizations and processor features of the latter. The key idea is to translate the assembler generated by a target compiler to an "assembler-level", functionally equivalent, C code. This code, annotated with timing and other execution related informations, is used as a very precise, yet fast, software simulation model. The approach is used in Cadence VCC, a system-level design environment. We report a comparison of several known approaches, the description of the new methodology, and experimental results, that show the effectiveness of the proposed method. We also propose several improvements.