Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889570
Tianjing Jiang, R. Klenke, J. Aylor, Gang Han
The test problem increasingly affects system design costs. One approach for reducing testing difficulties is to consider system testability as early as possible in the design cycle. The technique described herein adds a testability analysis capability to the ADEPT high-level performance modeling environment. This capability provides the designer with feedback on the testability of the specific architecture being modeled at an abstract level. The testability information is expressed in the form of measures of the relative controllability and observability of signals in the system architecture. The testability information is derived from reachability graph analysis of the corresponding Petri net representation of the system architecture. This methodology has the potential to provide valuable assistance in designing systems which have lower cost, higher performance, and which also meet testability requirements.
{"title":"System level testability analysis using Petri nets","authors":"Tianjing Jiang, R. Klenke, J. Aylor, Gang Han","doi":"10.1109/HLDVT.2000.889570","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889570","url":null,"abstract":"The test problem increasingly affects system design costs. One approach for reducing testing difficulties is to consider system testability as early as possible in the design cycle. The technique described herein adds a testability analysis capability to the ADEPT high-level performance modeling environment. This capability provides the designer with feedback on the testability of the specific architecture being modeled at an abstract level. The testability information is expressed in the form of measures of the relative controllability and observability of signals in the system architecture. The testability information is derived from reachability graph analysis of the corresponding Petri net representation of the system architecture. This methodology has the potential to provide valuable assistance in designing systems which have lower cost, higher performance, and which also meet testability requirements.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125347007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889565
A. Hajjar, Tom Chen, A. Andrews
During behavioral model verification, it is important to determine the stopping point for the current test strategy and for moving to a different test strategy. It has been shown that the location of the stopping point is highly dependent on the statistical model one should choose to describe the coverage behavior during the verification process. This paper presents a study on the coverage behavior of VHDL models. The resulting statistical behavior is compared to the statistical behavior used by some commonly used models for software reliability and shows the inappropriateness of applying the existing models for the behavior model verification.
{"title":"On statistical behavior of branch coverage in testing behavioral VHDL models","authors":"A. Hajjar, Tom Chen, A. Andrews","doi":"10.1109/HLDVT.2000.889565","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889565","url":null,"abstract":"During behavioral model verification, it is important to determine the stopping point for the current test strategy and for moving to a different test strategy. It has been shown that the location of the stopping point is highly dependent on the statistical model one should choose to describe the coverage behavior during the verification process. This paper presents a study on the coverage behavior of VHDL models. The resulting statistical behavior is compared to the statistical behavior used by some commonly used models for software reliability and shows the inappropriateness of applying the existing models for the behavior model verification.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122453309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889566
Hajime Yamashita, H. Yasuura, E. Fajar, Yun Cao
Variable size analysis is a technique to analyze the maximum bit length of each variable in a program or an HDL description. In design of an embedded system, the size (bit length) of each variable strongly affects the size of hardware (the width of datapath and the size of memory) and power consumption of the system. In this paper, we discuss practical methods of variable size analysis in combination of the static approach and simulation based dynamic approach. The variable size analysis is also applicable to design of multimedia embedded systems. Quality of computation of the system is determined by the trade-off between quality of output and cost of systems. We also proposed a new design called quality driven design methodology based on the variable size analysis.
{"title":"Variable size analysis and validation of computation quality","authors":"Hajime Yamashita, H. Yasuura, E. Fajar, Yun Cao","doi":"10.1109/HLDVT.2000.889566","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889566","url":null,"abstract":"Variable size analysis is a technique to analyze the maximum bit length of each variable in a program or an HDL description. In design of an embedded system, the size (bit length) of each variable strongly affects the size of hardware (the width of datapath and the size of memory) and power consumption of the system. In this paper, we discuss practical methods of variable size analysis in combination of the static approach and simulation based dynamic approach. The variable size analysis is also applicable to design of multimedia embedded systems. Quality of computation of the system is determined by the trade-off between quality of output and cost of systems. We also proposed a new design called quality driven design methodology based on the variable size analysis.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121885938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889575
H. Hsieh, F. Balarin
The synchronous assumption has made it possible to develop efficient procedures for establishing functional equivalence between different implementations in the domains of synchronous circuits and synchronous reactive systems. This notion is extended to embedded systems that do not satisfy the synchronous assumption inside their boundaries but only at the interface with the environment. Efficient, but conservative, synchronous equivalence analysis algorithms have been developed. In this work, we propose extensions to these algorithms that allow trading off the complexity with the conservativeness of the results.
{"title":"Refining abstract equivalence analysis for embedded system design","authors":"H. Hsieh, F. Balarin","doi":"10.1109/HLDVT.2000.889575","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889575","url":null,"abstract":"The synchronous assumption has made it possible to develop efficient procedures for establishing functional equivalence between different implementations in the domains of synchronous circuits and synchronous reactive systems. This notion is extended to embedded systems that do not satisfy the synchronous assumption inside their boundaries but only at the interface with the environment. Efficient, but conservative, synchronous equivalence analysis algorithms have been developed. In this work, we propose extensions to these algorithms that allow trading off the complexity with the conservativeness of the results.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"54 s53","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132359300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889580
C. Hansen, W. Rosenstiel
In the high-level synthesis (HLS) domain, more and more often the simulation vectors are specified at algorithmic level focussing on functional behavior. Due to the HLS and the inherent changes of the cycle-by-cycle behavior, simulation vector sets (SVS) specifying synchronous behavior cannot be reused on register transfer level (RTL). An automatic transformation of the algorithmic SVS is necessary to avoid a manual and time-consuming transformation phase. One critical part of the transformation process is to determine the mapping of the I/O operations of the algorithmic specification and of the I/O operations of the algorithmic SVS. Therefore, this paper presents three alternatives to solve this mapping problem, and describes their advantages, as well as their disadvantages.
{"title":"Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations","authors":"C. Hansen, W. Rosenstiel","doi":"10.1109/HLDVT.2000.889580","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889580","url":null,"abstract":"In the high-level synthesis (HLS) domain, more and more often the simulation vectors are specified at algorithmic level focussing on functional behavior. Due to the HLS and the inherent changes of the cycle-by-cycle behavior, simulation vector sets (SVS) specifying synchronous behavior cannot be reused on register transfer level (RTL). An automatic transformation of the algorithmic SVS is necessary to avoid a manual and time-consuming transformation phase. One critical part of the transformation process is to determine the mapping of the I/O operations of the algorithmic specification and of the I/O operations of the algorithmic SVS. Therefore, this paper presents three alternatives to solve this mapping problem, and describes their advantages, as well as their disadvantages.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131611855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889577
F. Wolf, R. Ernst
Accurate cache modeling and analysis are crucial to formally determine program execution time. Current cache analysis techniques combine basic block level cache modeling with explicit or implicit program path analysis. We show how to extend program and data cache modeling from basic blocks to program segments thereby increasing the overall execution time analysis precision. The approach combines architecture simulation, data flow analysis and implicit path enumeration.
{"title":"Data flow based cache prediction using local simulation","authors":"F. Wolf, R. Ernst","doi":"10.1109/HLDVT.2000.889577","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889577","url":null,"abstract":"Accurate cache modeling and analysis are crucial to formally determine program execution time. Current cache analysis techniques combine basic block level cache modeling with explicit or implicit program path analysis. We show how to extend program and data cache modeling from basic blocks to program segments thereby increasing the overall execution time analysis precision. The approach combines architecture simulation, data flow analysis and implicit path enumeration.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122137118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889552
V. Vedula, J. Abraham
The increasing functionality of processor designs has posed a severe challenge for generating high quality manufacturing tests, which can be applied at native speeds. A previous approach was to target one module at a time and extract functional constraints on the module under test (MUT) in order to reduce the complexity for test generation. However, when this technique is applied to large designs, the embedded modules themselves become too complex for an ATPG tool to handle. If sub-modules within these complex modules are considered, the extraction of constraints may prove to be too tedious. In this paper, a novel methodology to extract constraints hierarchically is presented. We use synthesis tools to eliminate redundant logic during the constraint extraction process. The proposed methodology also facilitates the reuse of constraints extracted for different sub-modules at a given level of hierarchy. This technique was applied to the ALU unit of the ARM Verilog benchmark design, and the results presented show that this technique makes the constraint extraction process more useful for large designs.
{"title":"A novel methodology for hierarchical test generation using functional constraint composition","authors":"V. Vedula, J. Abraham","doi":"10.1109/HLDVT.2000.889552","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889552","url":null,"abstract":"The increasing functionality of processor designs has posed a severe challenge for generating high quality manufacturing tests, which can be applied at native speeds. A previous approach was to target one module at a time and extract functional constraints on the module under test (MUT) in order to reduce the complexity for test generation. However, when this technique is applied to large designs, the embedded modules themselves become too complex for an ATPG tool to handle. If sub-modules within these complex modules are considered, the extraction of constraints may prove to be too tedious. In this paper, a novel methodology to extract constraints hierarchically is presented. We use synthesis tools to eliminate redundant logic during the constraint extraction process. The proposed methodology also facilitates the reuse of constraints extracted for different sub-modules at a given level of hierarchy. This technique was applied to the ALU unit of the ARM Verilog benchmark design, and the results presented show that this technique makes the constraint extraction process more useful for large designs.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128348969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889576
Michael D. Jones, G. Gopalakrishnan
We have used various manual abstraction techniques to formally verify a transaction ordering property for an IO protocol over bus/bridge networks. In the context of network protocol verification, an abstraction is needed to reduce the unbounded number of network configurations to a small number of representative networks that can be checked using algorithmic methods. The manually derived abstraction was both brittle and difficult to validate. In this report, we discuss the need for abstraction techniques in the formal verification of protocols over networks and present our recent efforts to create an automatic abstraction technique for network protocols using predicate abstraction as a starting point.
{"title":"Toward automated abstraction for protocols on branching networks","authors":"Michael D. Jones, G. Gopalakrishnan","doi":"10.1109/HLDVT.2000.889576","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889576","url":null,"abstract":"We have used various manual abstraction techniques to formally verify a transaction ordering property for an IO protocol over bus/bridge networks. In the context of network protocol verification, an abstraction is needed to reduce the unbounded number of network configurations to a small number of representative networks that can be checked using algorithmic methods. The manually derived abstraction was both brittle and difficult to validate. In this report, we discuss the need for abstraction techniques in the formal verification of protocols over networks and present our recent efforts to create an automatic abstraction technique for network protocols using predicate abstraction as a starting point.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114548063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889556
M. Pflanz, C. Galke, H. Vierhaus
In this paper we propose an efficient method to observe a processor state machine and to detect illegal states within one clock-cycle. The strategy is based on a comparison of an encoded vector VCP1, representing the real state, and a predicted vector YCP2, representing the expected state. The practical applicability of the concept was evaluated on several experimental processor designs. We implemented check-units for 8-, I6- and 32-bit microprocessors and DSPs with sets of 32 up to 214 instructions and a deterministic control-flow. The applicability to processors with a higher complexity is demonstrated by a check unit for state machine on-line observation of a pipelined microprocessor with superscalar data-path and hardware-implemented hazard control. To minimize the overhead we investigated different strategies to modify check units. A reduction of hardware overhead can be reached by application specific reduction of processor state machines. For more complex processors we propose a reduction of the overhead by partitioning of the state space.
{"title":"A new method for on-line state machine observation for embedded microprocessors","authors":"M. Pflanz, C. Galke, H. Vierhaus","doi":"10.1109/HLDVT.2000.889556","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889556","url":null,"abstract":"In this paper we propose an efficient method to observe a processor state machine and to detect illegal states within one clock-cycle. The strategy is based on a comparison of an encoded vector VCP1, representing the real state, and a predicted vector YCP2, representing the expected state. The practical applicability of the concept was evaluated on several experimental processor designs. We implemented check-units for 8-, I6- and 32-bit microprocessors and DSPs with sets of 32 up to 214 instructions and a deterministic control-flow. The applicability to processors with a higher complexity is demonstrated by a check unit for state machine on-line observation of a pipelined microprocessor with superscalar data-path and hardware-implemented hazard control. To minimize the overhead we investigated different strategies to modify check units. A reduction of hardware overhead can be reached by application specific reduction of processor state machines. For more complex processors we propose a reduction of the overhead by partitioning of the state space.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-08DOI: 10.1109/HLDVT.2000.889578
Jürgen Ruf, D. W. Hoffmann, T. Kropf, W. Rosenstiel
The verification of systems, i.e., hardware or hardware/software systems, is an important task in the design process. More than 70% of the development time is spend for locating and correcting error in the design. Therefore, many techniques have been proposed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However, their industrial applicability is curl-entry restricted to small or medium sized designs of to a specific phase in the design cycle. In this paper, we present a method for verifying temporal properties of systems described in an executable description language. Our method allows the user to specify properties about the system in finite linear time temporal logic (FLTL). These properties are checked on-the-fly during each simulation run, and each violation is immediately indicated to the designer.
{"title":"Checking temporal properties under simulation of executable system descriptions","authors":"Jürgen Ruf, D. W. Hoffmann, T. Kropf, W. Rosenstiel","doi":"10.1109/HLDVT.2000.889578","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889578","url":null,"abstract":"The verification of systems, i.e., hardware or hardware/software systems, is an important task in the design process. More than 70% of the development time is spend for locating and correcting error in the design. Therefore, many techniques have been proposed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However, their industrial applicability is curl-entry restricted to small or medium sized designs of to a specific phase in the design cycle. In this paper, we present a method for verifying temporal properties of systems described in an executable description language. Our method allows the user to specify properties about the system in finite linear time temporal logic (FLTL). These properties are checked on-the-fly during each simulation run, and each violation is immediately indicated to the designer.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131316080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：