Grzegorz Mrugalski, J. Rajski, J. Solecki, J. Tyszer, Chen Wang
{"title":"TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm","authors":"Grzegorz Mrugalski, J. Rajski, J. Solecki, J. Tyszer, Chen Wang","doi":"10.1109/ATS.2015.11","DOIUrl":null,"url":null,"abstract":"This paper presents a novel scan-based DFT paradigm. Compared to conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage, or allows applying much larger number of vectors within the same time interval. An equally important factor is the power dissipated during test - with the new scheme it remains similar to that of the mission mode. Several techniques are introduced that allow easy integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. Experimental results obtained for large and complex industrial ASIC designs illustrate feasibility of the proposed test schemes and are reported herein.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 24th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2015.11","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper presents a novel scan-based DFT paradigm. Compared to conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage, or allows applying much larger number of vectors within the same time interval. An equally important factor is the power dissipated during test - with the new scheme it remains similar to that of the mission mode. Several techniques are introduced that allow easy integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. Experimental results obtained for large and complex industrial ASIC designs illustrate feasibility of the proposed test schemes and are reported herein.