IO buffer for high performance, low-power application

Abstract

An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.8 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs.