{"title":"Alternative package-on-package with organic substrate interposer for stacking packaging solution","authors":"Steven Lin, M. Liao, Albert Lan, Davidlion Wang","doi":"10.1109/EPTC.2014.7028323","DOIUrl":null,"url":null,"abstract":"Package-on-Package (PoP) is an integrated circuit packaging method to vertically combine discrete logic device and low power mobile memory packages. Two chip scale BGA packages are installed atop each other, i.e. stacked, with a specific interface to route signals between them. This allows higher component density in devices, such as smart phone and tablet hand held products for bottom FCCSP digital Apps Processor, Modem, to stack with top Wire Bond LPPDDR CSP. The bottom FCCSP package form factor and its pin up of top solder balls were limited by LPDDR BGA matrix which had been defined by JEDEC. Due to high bandwidth memory requirement in smart phone, a lot of new PoP package solutions to accommodate more I/Os between top LPDDR memory package and bottom digital application processor package are booming up recently.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"9 12","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2014.7028323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Package-on-Package (PoP) is an integrated circuit packaging method to vertically combine discrete logic device and low power mobile memory packages. Two chip scale BGA packages are installed atop each other, i.e. stacked, with a specific interface to route signals between them. This allows higher component density in devices, such as smart phone and tablet hand held products for bottom FCCSP digital Apps Processor, Modem, to stack with top Wire Bond LPPDDR CSP. The bottom FCCSP package form factor and its pin up of top solder balls were limited by LPDDR BGA matrix which had been defined by JEDEC. Due to high bandwidth memory requirement in smart phone, a lot of new PoP package solutions to accommodate more I/Os between top LPDDR memory package and bottom digital application processor package are booming up recently.