Pub Date : 2014-12-03DOI: 10.1109/EPTC.2014.7028340
H. Liu, A. Lewis, S. H. Pu, L. Jiang, J. McBride
Gold coated Multi-Walled Carbon Nanotube (MWCNT) composites have been used for electrical contact surfaces in previous studies. It was shown that the composite could significantly improve switch lifetime, and exhibited potential as a useful contact material for MEMS switches. The reason is attributed to the contribution of the compressibility of the MWCNT forest, which creates a compliant layer under the gold films. In this study, experiments were performed for samples with different heights of MWCNT forests, namely 30 μm, 50 μm and 80 μm. The influence of MWCNT height on the switching behavior and lifetime were studied. An outcome of the work was that the sample with 80 μm height forests showed the longest lifetime, however the composites with 30 μm and 50 μm forest heights showed lower contact resistances, a parameter of high importance for MEMS switch applications.
{"title":"Influence of the height of Carbon Nanotubes on hot switching of Au/Cr-Au/MWCNT contact pairs","authors":"H. Liu, A. Lewis, S. H. Pu, L. Jiang, J. McBride","doi":"10.1109/EPTC.2014.7028340","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028340","url":null,"abstract":"Gold coated Multi-Walled Carbon Nanotube (MWCNT) composites have been used for electrical contact surfaces in previous studies. It was shown that the composite could significantly improve switch lifetime, and exhibited potential as a useful contact material for MEMS switches. The reason is attributed to the contribution of the compressibility of the MWCNT forest, which creates a compliant layer under the gold films. In this study, experiments were performed for samples with different heights of MWCNT forests, namely 30 μm, 50 μm and 80 μm. The influence of MWCNT height on the switching behavior and lifetime were studied. An outcome of the work was that the sample with 80 μm height forests showed the longest lifetime, however the composites with 30 μm and 50 μm forest heights showed lower contact resistances, a parameter of high importance for MEMS switch applications.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133955267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028353
G. Khatibi, B. Czerny, J. Magnien, M. Lederer, E. Suhir, J. Nicolics
Electronic product manufacturers are constantly seeking efficient, cost-effective and trustworthy accelerated test (AT) methods to keep up with the today's market demands. At present, accelerated temperature cycling testing is viewed as the state of the art for reliability assessment of electronic products. Accelerated mechanical fatigue testing has been proposed recently as a novel concept and an attractive cost-effective and time-saving qualification alternative for electronic devices. The principle idea of this approach is replacement of thermally induced loading with equivalent and adequate mechanical loading. Using mechanical fatigue testing set-ups, the devices under test can be subjected to single or multi-axial cyclic loading conditions at high frequencies. As a result, physically meaningful lifetime curves can be obtained. The suggested methodologies and procedures enable one to detect the vulnerable sites of the devices in a very short time. Exemplary results for power semiconductor products demonstrate the applicability of the proposed method for qualification of first and second level interconnects. The advantages and limitations of the proposed concept are addressed and discussed in detail.
{"title":"Towards adequate qualification testing of electronic products: Review and extension","authors":"G. Khatibi, B. Czerny, J. Magnien, M. Lederer, E. Suhir, J. Nicolics","doi":"10.1109/EPTC.2014.7028353","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028353","url":null,"abstract":"Electronic product manufacturers are constantly seeking efficient, cost-effective and trustworthy accelerated test (AT) methods to keep up with the today's market demands. At present, accelerated temperature cycling testing is viewed as the state of the art for reliability assessment of electronic products. Accelerated mechanical fatigue testing has been proposed recently as a novel concept and an attractive cost-effective and time-saving qualification alternative for electronic devices. The principle idea of this approach is replacement of thermally induced loading with equivalent and adequate mechanical loading. Using mechanical fatigue testing set-ups, the devices under test can be subjected to single or multi-axial cyclic loading conditions at high frequencies. As a result, physically meaningful lifetime curves can be obtained. The suggested methodologies and procedures enable one to detect the vulnerable sites of the devices in a very short time. Exemplary results for power semiconductor products demonstrate the applicability of the proposed method for qualification of first and second level interconnects. The advantages and limitations of the proposed concept are addressed and discussed in detail.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123100073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028314
E. Chen, Albert Lan, Jack You, M. Liao
In recent years mobile devices are getting more and more involved in to our daily life. With the requirement of IC packages inside mobile devices toward smaller form factor, low cost with high performance, a coreless substrate technology, naming Embedded Trace Substrate (ETS) is developed to meet market requirement and it has been studied in this paper. For an IC package with coreless substrate, warpage performance is a concern comparing to non-coreless substrate package of which has better substrate strength to balance Coefficients of Thermal Expansion (CTE) mismatch from molding compound. A Flip Chip Chip Scale Package (FCCSP) with body size 12×12mm is used as a test vehicle for this study and molding underfill (MUF) structure is selected to reduce package cost of additional underfill material. To evaluate the warpage performance of the ETS coreless substrate, finite element analysis simulation tool is used to compare package warpage for room temperature and high temperature. Also experimental validation of warpage is done by Shadow Moire test equipment. The study matrix includes different molding compound materials, molding compound thicknesses, substrate designs, substrate thicknesses, die thicknesses. By simulation and Shadow Moire measurement results can help the package structure and molding compound material selection that with thicker molding compound thickness, die thickness and substrate thickness have better warpage performance. In addition to warpage, the reliability performance is also evaluated for package under different test conditions such as assembly out time zero, uHAST, TCT and HTST. The evaluation index is Open/Short yield and failure analysis is also done for the O/S failed samples to evaluate failure rate, failure mode and failure locations. In the end, a package structure and bill of material (BOM) selection is finalized to have suitable warpage performance that meets requirement and can also pass reliability criteria.
{"title":"Structure reliability and characterization for FC package w/Embedded Trace coreless Substrate","authors":"E. Chen, Albert Lan, Jack You, M. Liao","doi":"10.1109/EPTC.2014.7028314","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028314","url":null,"abstract":"In recent years mobile devices are getting more and more involved in to our daily life. With the requirement of IC packages inside mobile devices toward smaller form factor, low cost with high performance, a coreless substrate technology, naming Embedded Trace Substrate (ETS) is developed to meet market requirement and it has been studied in this paper. For an IC package with coreless substrate, warpage performance is a concern comparing to non-coreless substrate package of which has better substrate strength to balance Coefficients of Thermal Expansion (CTE) mismatch from molding compound. A Flip Chip Chip Scale Package (FCCSP) with body size 12×12mm is used as a test vehicle for this study and molding underfill (MUF) structure is selected to reduce package cost of additional underfill material. To evaluate the warpage performance of the ETS coreless substrate, finite element analysis simulation tool is used to compare package warpage for room temperature and high temperature. Also experimental validation of warpage is done by Shadow Moire test equipment. The study matrix includes different molding compound materials, molding compound thicknesses, substrate designs, substrate thicknesses, die thicknesses. By simulation and Shadow Moire measurement results can help the package structure and molding compound material selection that with thicker molding compound thickness, die thickness and substrate thickness have better warpage performance. In addition to warpage, the reliability performance is also evaluated for package under different test conditions such as assembly out time zero, uHAST, TCT and HTST. The evaluation index is Open/Short yield and failure analysis is also done for the O/S failed samples to evaluate failure rate, failure mode and failure locations. In the end, a package structure and bill of material (BOM) selection is finalized to have suitable warpage performance that meets requirement and can also pass reliability criteria.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"8 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120860114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028392
Gu Bin, Jun Dimaano, Richen Chen, E. Bool, S. F. Shi, Choon Ghee Ang, N. Suthiwongsunthorn
The package warpage induced by residual stresses during molding process is one of the major thermo-mechanical reliability concerns in IC packaging. This paper proposes a method to find solution to unit warpage control with universal die thickness that ranges from 40 um to 250 um for the large FPBGA package. Firstly, the effect of each factor (mold cap thickness, substrate thickness, mold compound and die attach material) on warpage with these various die thickness was simulated and discussed. Then both tests and FEM simulations were conducted for few legs. The FEM simulation results were correlated with actual tests to determine the crying and smiling warpage boundary for satisfying warpage requirement in simulation. Based on actual tests and simulation results, three mold compounds (high CTE, middle CTE, low CTE), three mold cap thickness and two substrate thickness were selected to make full DoE simulation. Final simulation results showed that several combinations of mold cap thickness, substrate thickness and mold compound could be the solution to the warpage requirements with universal die thickness. Only a few more actual tests are needed to verify the final solution based on the simulation results.
{"title":"Unit warpage control with universal die thickness","authors":"Gu Bin, Jun Dimaano, Richen Chen, E. Bool, S. F. Shi, Choon Ghee Ang, N. Suthiwongsunthorn","doi":"10.1109/EPTC.2014.7028392","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028392","url":null,"abstract":"The package warpage induced by residual stresses during molding process is one of the major thermo-mechanical reliability concerns in IC packaging. This paper proposes a method to find solution to unit warpage control with universal die thickness that ranges from 40 um to 250 um for the large FPBGA package. Firstly, the effect of each factor (mold cap thickness, substrate thickness, mold compound and die attach material) on warpage with these various die thickness was simulated and discussed. Then both tests and FEM simulations were conducted for few legs. The FEM simulation results were correlated with actual tests to determine the crying and smiling warpage boundary for satisfying warpage requirement in simulation. Based on actual tests and simulation results, three mold compounds (high CTE, middle CTE, low CTE), three mold cap thickness and two substrate thickness were selected to make full DoE simulation. Final simulation results showed that several combinations of mold cap thickness, substrate thickness and mold compound could be the solution to the warpage requirements with universal die thickness. Only a few more actual tests are needed to verify the final solution based on the simulation results.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"603 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028298
Leong Yew Wing, Zhang Shiyun, Christopher Pang, Mohammad Hazren, Sunil Kumar, W. C. Chung
Increasing demand for faster and more accurate diagnostic procedures has sparked trends in the development of electrochemical sensors for biology research and medical diagnostics. Inter-digitated electrode based electrochemical sensors have shown higher sensitivity and label-free approach to medical diagnostics. This paper presents a comparative study on the different lift-off methods which were used in the fabrication of high density gold inter-digitated electrodes (IDE) for electrochemical detection. The paper focuses on the generation of “T-Topped” resist profile also known as re-entrance resist profile which facilitates efficient metal lift-off after deposition. IDE with thickness of 30nm Ti and 200nm gold electrodes with 5μm line width and a pitch of 15μm were patterned on an 8” silicon substrate insulated with thermal oxide film. The detailed fabrication processes, the adhesion enhancement strategies, and accounts for the merits and limitation of each proposed fabrication technique are presented. Lastly, the impact of different expose dose on the final critical dimension (CD) of the electrochemical sensors was investigated.
{"title":"Optimization studies of lift-off methods and its application in electrochemical biosensors","authors":"Leong Yew Wing, Zhang Shiyun, Christopher Pang, Mohammad Hazren, Sunil Kumar, W. C. Chung","doi":"10.1109/EPTC.2014.7028298","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028298","url":null,"abstract":"Increasing demand for faster and more accurate diagnostic procedures has sparked trends in the development of electrochemical sensors for biology research and medical diagnostics. Inter-digitated electrode based electrochemical sensors have shown higher sensitivity and label-free approach to medical diagnostics. This paper presents a comparative study on the different lift-off methods which were used in the fabrication of high density gold inter-digitated electrodes (IDE) for electrochemical detection. The paper focuses on the generation of “T-Topped” resist profile also known as re-entrance resist profile which facilitates efficient metal lift-off after deposition. IDE with thickness of 30nm Ti and 200nm gold electrodes with 5μm line width and a pitch of 15μm were patterned on an 8” silicon substrate insulated with thermal oxide film. The detailed fabrication processes, the adhesion enhancement strategies, and accounts for the merits and limitation of each proposed fabrication technique are presented. Lastly, the impact of different expose dose on the final critical dimension (CD) of the electrochemical sensors was investigated.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123026137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028358
S. Lahokallio, L. Frisk
This paper studies the high temperature performance and reliability of electrically conductive adhesive (ECA) attached temperature sensors. Testing of the sensors was conducted using a high temperature cycling test with long transition time between the extreme temperatures of -55°C and +180°C. Several different ECA materials were used as attachment materials. Additionally, the effects of the thickness and material of a substrate were studied. Real-time measurements were conducted during testing and these showed that ECA interconnections could withstand harsh high temperature cycling for long periods of time when proper materials and structures were chosen. Significant differences between the ECA materials were seen, thus the selection of the ECA material was found to be very important for the interconnection reliability. Additionally, the thickness and material of the substrate had a marked effect on the reliability. In most cases a flexible substrate yielded a better performance, but the effect differed between the ECA materials. The ECAs studied were mostly anisotropic conductive adhesives (ACAs). However, two isotropically conductive adhesives (ICAs) were also studied, one of them also with an underfill. Although underfill material is commonly used with ICAs, in this study it was observed to impair the reliability. The results showed that analysis of the reliability of all materials and structures is essential when adhesives are used in high temperature applications.
{"title":"Performance of electrically conductive adhesive attached sensors in high temperature cycling","authors":"S. Lahokallio, L. Frisk","doi":"10.1109/EPTC.2014.7028358","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028358","url":null,"abstract":"This paper studies the high temperature performance and reliability of electrically conductive adhesive (ECA) attached temperature sensors. Testing of the sensors was conducted using a high temperature cycling test with long transition time between the extreme temperatures of -55°C and +180°C. Several different ECA materials were used as attachment materials. Additionally, the effects of the thickness and material of a substrate were studied. Real-time measurements were conducted during testing and these showed that ECA interconnections could withstand harsh high temperature cycling for long periods of time when proper materials and structures were chosen. Significant differences between the ECA materials were seen, thus the selection of the ECA material was found to be very important for the interconnection reliability. Additionally, the thickness and material of the substrate had a marked effect on the reliability. In most cases a flexible substrate yielded a better performance, but the effect differed between the ECA materials. The ECAs studied were mostly anisotropic conductive adhesives (ACAs). However, two isotropically conductive adhesives (ICAs) were also studied, one of them also with an underfill. Although underfill material is commonly used with ICAs, in this study it was observed to impair the reliability. The results showed that analysis of the reliability of all materials and structures is essential when adhesives are used in high temperature applications.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122072066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028321
A. Lin, Vincent Chen, J. Chen, Simon Leou, Thomas Wang, Harrison Chang
This paper describes the performance characterization for a novel compartment shielding process. The CPS process is developed for molded base SiP module which can form multiple arbitrary shape shielded areas. This compartment shielding structure not only occupies the smallest space itself, the good shielding performance can reduce the leakage and increase more placement area by shortening the keep out distance at the sides and edges near the wall between compartments. It reduces the interference between shielded sub-circuits e.g. digital, analog and RF circuits. The compartment shielding structure is seamlessly connected to the grounding of the substrate, hence has superior isolation performance. The shielding wall which isolates the compartments is made by laser scribing and trench filling. First the model of geometry of CPS wall is built up, boundary condition is set and material parameters are assigned. SE performance of CPS is simulated by HFSS software using Finite Element Method (FEM). Manual Mesh is used to improve the accuracy of simulation. Visualized 3D EM field is extracted for analyzing how and to what extent the defects of process degrading the SE. Besides the shielding effectiveness, the conductivity of filling material and the contact resistance between that material and ground pad beneath the CPS trench is studied and correlated to the shielding performance. Finally we improve the shielding performance of CPS and the simulation model we built up is close to measurement. Moreover, a LTE modem with two shielding trenches is made and its performance is verified. This single mode/dual bands LTE modem module with three compartments accommodate digital, RF Tx and RF Rx circuit with size 23×26×1.9 mm only. The RF performance of this modem is excellent, and meets all 3GPP LTE Category 3 and carrier's requirements, passes FCC/CE EMI, GCF and PTCRB certification. It is found that this compartment shielding process is good for consumer grade SiP module both in technology and in commercial terms.
{"title":"Electrical performance characterization for novel multiple compartments shielding and verification on LTE modem SiP","authors":"A. Lin, Vincent Chen, J. Chen, Simon Leou, Thomas Wang, Harrison Chang","doi":"10.1109/EPTC.2014.7028321","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028321","url":null,"abstract":"This paper describes the performance characterization for a novel compartment shielding process. The CPS process is developed for molded base SiP module which can form multiple arbitrary shape shielded areas. This compartment shielding structure not only occupies the smallest space itself, the good shielding performance can reduce the leakage and increase more placement area by shortening the keep out distance at the sides and edges near the wall between compartments. It reduces the interference between shielded sub-circuits e.g. digital, analog and RF circuits. The compartment shielding structure is seamlessly connected to the grounding of the substrate, hence has superior isolation performance. The shielding wall which isolates the compartments is made by laser scribing and trench filling. First the model of geometry of CPS wall is built up, boundary condition is set and material parameters are assigned. SE performance of CPS is simulated by HFSS software using Finite Element Method (FEM). Manual Mesh is used to improve the accuracy of simulation. Visualized 3D EM field is extracted for analyzing how and to what extent the defects of process degrading the SE. Besides the shielding effectiveness, the conductivity of filling material and the contact resistance between that material and ground pad beneath the CPS trench is studied and correlated to the shielding performance. Finally we improve the shielding performance of CPS and the simulation model we built up is close to measurement. Moreover, a LTE modem with two shielding trenches is made and its performance is verified. This single mode/dual bands LTE modem module with three compartments accommodate digital, RF Tx and RF Rx circuit with size 23×26×1.9 mm only. The RF performance of this modem is excellent, and meets all 3GPP LTE Category 3 and carrier's requirements, passes FCC/CE EMI, GCF and PTCRB certification. It is found that this compartment shielding process is good for consumer grade SiP module both in technology and in commercial terms.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028370
Hengyun Zhang, How Yuan Hwang, L. Bu, Jerry Jie Li Aw, D. Rhee
Silicon carbide based power modules are receiving more attention due to their performance advantages over traditional silicon power modules. The demanding operation requirements such as higher power output, faster switching speed, and higher working temperature present great thermal management challenge, which necessitates the analysis and characterization of various thermal interface and bonding layers and cooling technologies. In the present work, a new 3-phase SiC DMOSFET power module is developed with six SiC dies and copper clips, and corresponding cooling technologies are examined under liquid cooling and air cooling conditions. Different thermal assembly layers including flip chip attach, clip attach, direct bonding copper (DBC), heat sink thermal interface materials are examined. It is found that the die attach and clip attach, formed with sintering silver, have the most significant effects on the power module thermal performance than the outer heat sink thermal interface materials. In addition, the die metallization size should be enlarged as much as possible to minimize the internal thermal resistance at flip chip bonding layer. A module thermal resistance is found to be 0.184 K/W under dual side liquid cooling and 0.254 K/W under air cooling condition. A liquid cooled heat sink is fabricated with ceramic based copper fins. A power cycling simulation is also conducted, which indicate that a junction temperature change (ΔT) of 150°C could be attained with 1.5S/1.5S on/off condition and 960 W power input.
{"title":"Thermal modeling and characterization of SiC power module under both air cooling and liquid cooling conditions","authors":"Hengyun Zhang, How Yuan Hwang, L. Bu, Jerry Jie Li Aw, D. Rhee","doi":"10.1109/EPTC.2014.7028370","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028370","url":null,"abstract":"Silicon carbide based power modules are receiving more attention due to their performance advantages over traditional silicon power modules. The demanding operation requirements such as higher power output, faster switching speed, and higher working temperature present great thermal management challenge, which necessitates the analysis and characterization of various thermal interface and bonding layers and cooling technologies. In the present work, a new 3-phase SiC DMOSFET power module is developed with six SiC dies and copper clips, and corresponding cooling technologies are examined under liquid cooling and air cooling conditions. Different thermal assembly layers including flip chip attach, clip attach, direct bonding copper (DBC), heat sink thermal interface materials are examined. It is found that the die attach and clip attach, formed with sintering silver, have the most significant effects on the power module thermal performance than the outer heat sink thermal interface materials. In addition, the die metallization size should be enlarged as much as possible to minimize the internal thermal resistance at flip chip bonding layer. A module thermal resistance is found to be 0.184 K/W under dual side liquid cooling and 0.254 K/W under air cooling condition. A liquid cooled heat sink is fabricated with ceramic based copper fins. A power cycling simulation is also conducted, which indicate that a junction temperature change (ΔT) of 150°C could be attained with 1.5S/1.5S on/off condition and 960 W power input.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128367608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028346
L. E. Khoong, T. K. Gan, M. B. Young
Silicone-based adhesive bond separations on polymer and ceramic-based samples were analyzed. Scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX), Fourier transform infra-red spectroscopy (FTIR) and Gas chromatography mass spectrometry (GCMS) analyses were conducted on surfaces of glass fiber reinforced polybutylene terephthalate (PBT) and aluminum nitride samples. Further surface analyses, i.e. surface contact angle measurement, X-ray photoelectron spectroscopy (XPS) and time of flight secondary ion mass spectrometry (TOF-SIMS) indicates that the adhesive bond separation could have been caused by excessive sulfur content on the PBT surface and excessive residual organic compound containing hydroxyl functional group on aluminum nitride surface. Potential separation mechanisms of the adhesive bond for these two case studies were also discussed.
{"title":"Analysis of silicone-based adhesive bond separation","authors":"L. E. Khoong, T. K. Gan, M. B. Young","doi":"10.1109/EPTC.2014.7028346","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028346","url":null,"abstract":"Silicone-based adhesive bond separations on polymer and ceramic-based samples were analyzed. Scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX), Fourier transform infra-red spectroscopy (FTIR) and Gas chromatography mass spectrometry (GCMS) analyses were conducted on surfaces of glass fiber reinforced polybutylene terephthalate (PBT) and aluminum nitride samples. Further surface analyses, i.e. surface contact angle measurement, X-ray photoelectron spectroscopy (XPS) and time of flight secondary ion mass spectrometry (TOF-SIMS) indicates that the adhesive bond separation could have been caused by excessive sulfur content on the PBT surface and excessive residual organic compound containing hydroxyl functional group on aluminum nitride surface. Potential separation mechanisms of the adhesive bond for these two case studies were also discussed.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124639739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028309
Wang Ai-Chie, Chong Chin Hui
As the speed performance of memory silicon die advances over the generations, the corresponding package designs must align with the desired package-level performance. This has driven package designers to adopt the appropriate package routing design practices for DDR2 to DDR4 DRAM and NV-DDR to NV-DDR2 NAND Flash memory packages that keep not only the mechanical integrity of the package in mind but also the electrical (signal integrity) aspects of the package. This paper describes the relevant package routing considerations for BOC and COB interposer designs with the goal of meeting the electrical requirements for high-speed devices; these results have been documented to ensure that these routing requirements are checked at the final design review stage to enable Micron to deliver quality products to customers.
{"title":"Considerations for package routing for DRAM and NAND Flash memory","authors":"Wang Ai-Chie, Chong Chin Hui","doi":"10.1109/EPTC.2014.7028309","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028309","url":null,"abstract":"As the speed performance of memory silicon die advances over the generations, the corresponding package designs must align with the desired package-level performance. This has driven package designers to adopt the appropriate package routing design practices for DDR2 to DDR4 DRAM and NV-DDR to NV-DDR2 NAND Flash memory packages that keep not only the mechanical integrity of the package in mind but also the electrical (signal integrity) aspects of the package. This paper describes the relevant package routing considerations for BOC and COB interposer designs with the goal of meeting the electrical requirements for high-speed devices; these results have been documented to ensure that these routing requirements are checked at the final design review stage to enable Micron to deliver quality products to customers.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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