Nearest neighbour interconnect architecture in deep submicron FPGAs

Abstract

Several commercial FPGA architectures provide fast connections between adjacent logic blocks that decrease the best-case delay between circuit elements with the goal of increasing overall performance. This paper explores the architecture of these Nearest Neighbour (NN) interconnects to determine topologies, quantities and distances that are best for performance and area. We show that certain architectures can achieve a 7.4% performance improvement at the cost of a 6.3% increase in total FPGA area when fully populated. We also show that a 6.4% improvement can be achieved for a more modest cost of 3.8% increase in area.