The effectiveness of IDDQ and high voltage stress for burn-in elimination [CMOS production]

Abstract

IDDQ testing has been introduced to CMOS production lines for achieving higher quality and reliability. In addition, electrical stress applying method called High Voltage Stress (HVS) method was proposed for reliable rejection of weak insulation (such as gate oxide and interlayer separators). The capability of IDDQ testing and HVS method for elimination of burn-in process, an effective method to guarantee reliability but expensive, was investigated. The reduction of burn-in failure rate of 1.0 /spl mu/m product by introducing IDDQ testing prior to burn-in indicated that burn-in elimination was possible. Based on this result, burn-in elimination was accomplished for 0.5 /spl mu/m products followed by HVS method adoption. Failure analysis on IDDQ rejects of 0.5 /spl mu/m products have clarified IDDQ+HVS as alternative cost effective technology of conventional burn-in. Further investigation revealed that even IDDQ+HVS was not effective enough for screening devices made from badly contaminated wafers.