Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557841
S. Makar, E. McCluskey
Fault Simulation results of different implementations of 2-1 multiplexers and D-latches are presented. These results show that some faults can only be detected by I/sub ddq/ test. Simulation results also show that the "importance" of I/sub ddq/ as a test method can vary considerably with implementation.
{"title":"Some faults need an I/sub ddq/ test","authors":"S. Makar, E. McCluskey","doi":"10.1109/IDDQ.1996.557841","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557841","url":null,"abstract":"Fault Simulation results of different implementations of 2-1 multiplexers and D-latches are presented. These results show that some faults can only be detected by I/sub ddq/ test. Simulation results also show that the \"importance\" of I/sub ddq/ as a test method can vary considerably with implementation.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557804
A. Gattiker, P. Nigh, D. Grosch, Wojciech Maly
The concept of the current signature has been proposed as a means for improving testing resolution over single-threshold Iddq testing. This paper postulates a practical methodology for applying the current signature concept for die selection in a production environment.
{"title":"Current signatures for production testing [CMOS ICs]","authors":"A. Gattiker, P. Nigh, D. Grosch, Wojciech Maly","doi":"10.1109/IDDQ.1996.557804","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557804","url":null,"abstract":"The concept of the current signature has been proposed as a means for improving testing resolution over single-threshold Iddq testing. This paper postulates a practical methodology for applying the current signature concept for die selection in a production environment.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133258937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557800
R. Kawahara, O. Nakayama, T. Kurasawa
IDDQ testing has been introduced to CMOS production lines for achieving higher quality and reliability. In addition, electrical stress applying method called High Voltage Stress (HVS) method was proposed for reliable rejection of weak insulation (such as gate oxide and interlayer separators). The capability of IDDQ testing and HVS method for elimination of burn-in process, an effective method to guarantee reliability but expensive, was investigated. The reduction of burn-in failure rate of 1.0 /spl mu/m product by introducing IDDQ testing prior to burn-in indicated that burn-in elimination was possible. Based on this result, burn-in elimination was accomplished for 0.5 /spl mu/m products followed by HVS method adoption. Failure analysis on IDDQ rejects of 0.5 /spl mu/m products have clarified IDDQ+HVS as alternative cost effective technology of conventional burn-in. Further investigation revealed that even IDDQ+HVS was not effective enough for screening devices made from badly contaminated wafers.
{"title":"The effectiveness of IDDQ and high voltage stress for burn-in elimination [CMOS production]","authors":"R. Kawahara, O. Nakayama, T. Kurasawa","doi":"10.1109/IDDQ.1996.557800","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557800","url":null,"abstract":"IDDQ testing has been introduced to CMOS production lines for achieving higher quality and reliability. In addition, electrical stress applying method called High Voltage Stress (HVS) method was proposed for reliable rejection of weak insulation (such as gate oxide and interlayer separators). The capability of IDDQ testing and HVS method for elimination of burn-in process, an effective method to guarantee reliability but expensive, was investigated. The reduction of burn-in failure rate of 1.0 /spl mu/m product by introducing IDDQ testing prior to burn-in indicated that burn-in elimination was possible. Based on this result, burn-in elimination was accomplished for 0.5 /spl mu/m products followed by HVS method adoption. Failure analysis on IDDQ rejects of 0.5 /spl mu/m products have clarified IDDQ+HVS as alternative cost effective technology of conventional burn-in. Further investigation revealed that even IDDQ+HVS was not effective enough for screening devices made from badly contaminated wafers.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"13 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557809
M. A. Ortega, J. Rius, J. Figueras
A modified Keating-Meyer technique to test CMOS circuits by measuring its energy consumption is presented. The circuit is fed by a capacitor being successively recharged while it is excited by a set of test vectors. A Binary Counter is incremented after a quantum of energy has been supplied to the CUT while the circuit is excited by test vectors. The energy cronogram for a given vector set is defined as its Energy Signature. Preliminary experiments show how this energy signature could be used to discriminate non-defective from defective circuits. If the test is applied at a sufficiently low rate the information obtained is equivalent to I/sub DDQ/ testing. Experimental data agree with predicted results and show how bridging and open faults are detected with this method.
{"title":"Test of CMOS circuits based on its energy consumption","authors":"M. A. Ortega, J. Rius, J. Figueras","doi":"10.1109/IDDQ.1996.557809","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557809","url":null,"abstract":"A modified Keating-Meyer technique to test CMOS circuits by measuring its energy consumption is presented. The circuit is fed by a capacitor being successively recharged while it is excited by a set of test vectors. A Binary Counter is incremented after a quantum of energy has been supplied to the CUT while the circuit is excited by test vectors. The energy cronogram for a given vector set is defined as its Energy Signature. Preliminary experiments show how this energy signature could be used to discriminate non-defective from defective circuits. If the test is applied at a sufficiently low rate the information obtained is equivalent to I/sub DDQ/ testing. Experimental data agree with predicted results and show how bridging and open faults are detected with this method.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131422182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557810
S. Millman, J. Acken
Industry needs to move from a separate step of design for test to solving test issues as an integral part of the design process. The linking of design and test is also needed for I/sub DDQ/ testing, which is required for high quality products. A key issue is how to set the I/sub DDQ/ current limit to detect defective parts without rejecting defect-free parts. Increasing design efforts for accurate standard cell library characterization, especially with respect to power provide the answer. This paper describes a method for setting the I/sub DDQ/ limit based upon cell library characterization. Additionally, the method for iterating in on the final values is reviewed and contrasted with the benefits of the new method.
{"title":"Standard cell library characterization for setting current limits for I/sub DDQ/ testing","authors":"S. Millman, J. Acken","doi":"10.1109/IDDQ.1996.557810","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557810","url":null,"abstract":"Industry needs to move from a separate step of design for test to solving test issues as an integral part of the design process. The linking of design and test is also needed for I/sub DDQ/ testing, which is required for high quality products. A key issue is how to set the I/sub DDQ/ current limit to detect defective parts without rejecting defect-free parts. Increasing design efforts for accurate standard cell library characterization, especially with respect to power provide the answer. This paper describes a method for setting the I/sub DDQ/ limit based upon cell library characterization. Additionally, the method for iterating in on the final values is reviewed and contrasted with the benefits of the new method.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129283795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557839
H. Manhaeve, M. Svajda, B. Straka
This paper presents some of the steps taken towards the design and realisation of a general-purpose fully digital I/sub DDQ/ monitor based upon the OCIMU circuit. It focuses in more detail on two of the possible implementation routes, the design and realisation of a programmable monitor, based on discrete components, and the design of a fully integrated monolithic version. Both circuits operate as a semi-digital monitor, are capable to drive a high capacitive load, can be used in combination with standard ATE, and are invisible to the DUT, so that its operation is not affected by the monitor. Both monitors are designed to measure currents up to 1 mA within a 10 kHz test cycle. The resolution of the discrete programmable current monitor is function of the configuration selected and its best value is 80 nA. Simulations of the monolithic version, implemented in 2 /spl mu/m BiCMOS technology show an accuracy better than 1 /spl mu/A, similar to the OCIMU circuit.
{"title":"Semi-digital off-chip I/sub DDQ/ monitor developments: towards a general-purpose digital current monitor","authors":"H. Manhaeve, M. Svajda, B. Straka","doi":"10.1109/IDDQ.1996.557839","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557839","url":null,"abstract":"This paper presents some of the steps taken towards the design and realisation of a general-purpose fully digital I/sub DDQ/ monitor based upon the OCIMU circuit. It focuses in more detail on two of the possible implementation routes, the design and realisation of a programmable monitor, based on discrete components, and the design of a fully integrated monolithic version. Both circuits operate as a semi-digital monitor, are capable to drive a high capacitive load, can be used in combination with standard ATE, and are invisible to the DUT, so that its operation is not affected by the monitor. Both monitors are designed to measure currents up to 1 mA within a 10 kHz test cycle. The resolution of the discrete programmable current monitor is function of the configuration selected and its best value is 80 nA. Simulations of the monolithic version, implemented in 2 /spl mu/m BiCMOS technology show an accuracy better than 1 /spl mu/A, similar to the OCIMU circuit.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"408 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116639950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557836
W. Xiaoqing, K. Saluja, K. Kinoshita, H. Tamamoto
This paper presents an innovative method of equivalence fault collapsing for the transistor leakage faults, a fault model often used in I/sub DDQ/ testing. The experimental results show the effectiveness of the proposed method in reducing the number of faults that have to be considered and its usefulness in I/sub DDQ/ testing.
{"title":"Equivalence fault collapsing for transistor leakage faults","authors":"W. Xiaoqing, K. Saluja, K. Kinoshita, H. Tamamoto","doi":"10.1109/IDDQ.1996.557836","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557836","url":null,"abstract":"This paper presents an innovative method of equivalence fault collapsing for the transistor leakage faults, a fault model often used in I/sub DDQ/ testing. The experimental results show the effectiveness of the proposed method in reducing the number of faults that have to be considered and its usefulness in I/sub DDQ/ testing.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121382484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557817
M. Sidiropulos, V. Stopjaková, H. Manhaeve
The last step in the development of a BIST structure employing a new self-test technique for analog circuits is presented in this paper, namely the design and implementation of a suitable built-in supply current (BIC) monitor. The new self-test technique based on power supply current monitoring, takes advantage of the redundancy in the structure of fully balanced circuits. The new technique requires a special BIC monitor that provides appropriate signals for a successful fault detection. The BIC monitor, presented in this paper, is based on a second generation current conveyor CCII+, and offers an accurate measurement of supply currents with a minimal supply voltage degradation. The BIC monitor circuit was evaluated using fault simulations, which show a reasonable fault coverage. An implementation of the new BIC monitor in an analog BIST structure is finally described.
{"title":"Implementation of a BIC monitor in a new analog BIST structure","authors":"M. Sidiropulos, V. Stopjaková, H. Manhaeve","doi":"10.1109/IDDQ.1996.557817","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557817","url":null,"abstract":"The last step in the development of a BIST structure employing a new self-test technique for analog circuits is presented in this paper, namely the design and implementation of a suitable built-in supply current (BIC) monitor. The new self-test technique based on power supply current monitoring, takes advantage of the redundancy in the structure of fully balanced circuits. The new technique requires a special BIC monitor that provides appropriate signals for a successful fault detection. The BIC monitor, presented in this paper, is based on a second generation current conveyor CCII+, and offers an accurate measurement of supply currents with a minimal supply voltage degradation. The BIC monitor circuit was evaluated using fault simulations, which show a reasonable fault coverage. An implementation of the new BIC monitor in an analog BIST structure is finally described.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124374312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557816
Chih-Wen Lu, Chung-Len Lee, Jwu-E Chen
In this work, a fast and highly sensitive Built-in Current (BIC) sensor is proposed for testing static CMOS ICs. The sensor employs a current mirror and an I-V converter to achieve the high sensing speed and high resolution. The circuit is simple and occupies a small area, making it ideal to be integrated into the IC chip for the IDDQ application.
{"title":"A fast and sensitive built-in current sensor for IDDQ testing","authors":"Chih-Wen Lu, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/IDDQ.1996.557816","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557816","url":null,"abstract":"In this work, a fast and highly sensitive Built-in Current (BIC) sensor is proposed for testing static CMOS ICs. The sensor employs a current mirror and an I-V converter to achieve the high sensing speed and high resolution. The circuit is simple and occupies a small area, making it ideal to be integrated into the IC chip for the IDDQ application.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121339613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-24DOI: 10.1109/IDDQ.1996.557840
L. Ribas-Xirgo, J. Carrabina-Bordoll
Test generation for logic faults can also be used to enable Iddq sensing devices detect a large number of Iddq-testable faults such as stuck-on transistors and line bridging. However, there are some of these faults not covered by the stuck-at fault model that need particular attention. In this paper, we present a method to generate test patterns for short-circuit faults with difficult equivalence for the gate-level stuck-at model. A symbolic simulation of a circuit having been injected a set of faults is performed to obtain its functional response, which is given as a set of functions in terms of input and fault-selection Boolean variables. Such functions are operated to obtain a minimal set of appropriate test vectors, which can be directly used as part of the final test set, or fed into a gate-level ATPG to improve the switch-level fault coverage of its resulting test patterns.
{"title":"Automatic test pattern generation for Iddq faults based upon symbolic simulation","authors":"L. Ribas-Xirgo, J. Carrabina-Bordoll","doi":"10.1109/IDDQ.1996.557840","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557840","url":null,"abstract":"Test generation for logic faults can also be used to enable Iddq sensing devices detect a large number of Iddq-testable faults such as stuck-on transistors and line bridging. However, there are some of these faults not covered by the stuck-at fault model that need particular attention. In this paper, we present a method to generate test patterns for short-circuit faults with difficult equivalence for the gate-level stuck-at model. A symbolic simulation of a circuit having been injected a set of faults is performed to obtain its functional response, which is given as a set of functions in terms of input and fault-selection Boolean variables. Such functions are operated to obtain a minimal set of appropriate test vectors, which can be directly used as part of the final test set, or fed into a gate-level ATPG to improve the switch-level fault coverage of its resulting test patterns.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127165734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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