A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2016-11-01 DOI:10.1109/ASSCC.2016.7844158

Mark Maddox, Baozhen Chen, M. Coln, Ron Kapusta, Junhua Shen, Lalinda D. Fernando

引用次数: 24

Abstract

This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed unique ADC architecture and calibration technique addresses the issue of signal dependent reference voltage droop during SAR ADC bit trials and orthogonalize the bit weights to achieve 16bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the bit cap, the first reported in this type of SAR ADC. Measurement result from a prototype test chip shows +/−0.8 LSB (16-bit level) INL at 1MSPS.

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基于55nm CMOS的16位线性无源电荷共享SAR ADC

本文提出了一种首次报道的无源电荷共享SAR ADC，实现了16位线性。众所周知，片上无源电荷共享由于在比特试验期间基准电压不稳定而导致线性度差。所提出的独特ADC架构和校准技术解决了SAR ADC位试验期间信号相关参考电压下降的问题，并将位权正交以实现16位线性。此外，所提出的架构通过采样到位帽来最大化信噪比，这是此类SAR ADC中首次报道的。来自原型测试芯片的测量结果显示，在1MSPS下，INL为+/−0.8 LSB(16位电平)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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