Pub Date : 2017-07-06DOI: 10.1109/JSSC.2017.2715160
Masum Hossain, W. El-Halwagy, A. D. Hossain, Aurangozeb
This paper presents a low power clocking solution for multi-standard SerDes applications based on frac-N digital LC PLL for central clock generation and fractional-N ring PLL for local clock generation. The fractional-N LC PLL operates at 7–10 GHz consuming only 8 mW power and occupying 0.15 mm2 of silicon area with integrated jitter of 264 fs. Ring PLL covers from 800 MHz to 4 GHz to support the data rates between 1 to 14 Gb/s. The ring PLL supports dither-less fractional resolution of 250 MHz, corrects I/Q error with split tuning and achieves less than 400 fs integrated jitter. Transmitter works at 14 Gb/s with power efficiency of 0.80 pJ/bit.
{"title":"Fractional-N DPLL based low power clocking architecture for 1–14 Gb/s multi-standard transmitter","authors":"Masum Hossain, W. El-Halwagy, A. D. Hossain, Aurangozeb","doi":"10.1109/JSSC.2017.2715160","DOIUrl":"https://doi.org/10.1109/JSSC.2017.2715160","url":null,"abstract":"This paper presents a low power clocking solution for multi-standard SerDes applications based on frac-N digital LC PLL for central clock generation and fractional-N ring PLL for local clock generation. The fractional-N LC PLL operates at 7–10 GHz consuming only 8 mW power and occupying 0.15 mm2 of silicon area with integrated jitter of 264 fs. Ring PLL covers from 800 MHz to 4 GHz to support the data rates between 1 to 14 Gb/s. The ring PLL supports dither-less fractional resolution of 250 MHz, corrects I/Q error with split tuning and achieves less than 400 fs integrated jitter. Transmitter works at 14 Gb/s with power efficiency of 0.80 pJ/bit.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123366240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-09DOI: 10.1109/ASSCC.2016.7844207
Zhe Chen, Hao Gao, D. Leenaerts, D. Milosevic, P. Baltus
This paper presents an ultra-broadband low-noise amplifier (LNA) operating from 16 to 43 GHz in a 0.25 pm SiGe:C BiCMOS technology. Across this band, the LNA achieves simultaneous low-noise performance (2.5–4.0 dB) and power matching (S11 < −10 dB) using dual-LC tank matching. The measured minimal noise figure is 2.5 dB at 26 GHz with an average value of 3.25 (±0.75) dB from 16 to 44 GHz. The best gain is 10.5 dB at 26 GHz with a 3-dB gain bandwidth from 16 to 43 GHz (90% fractional bandwidth). The measured input 1-dB compression point and input IP3 are better than −8.5 dBm and 1.8 dBm over the 16–43 GHz band, respectively, for a total power consumption of 24 mW.
{"title":"A 16–43 GHz low-noise amplifer with 2.5–4.0 dB noise figure","authors":"Zhe Chen, Hao Gao, D. Leenaerts, D. Milosevic, P. Baltus","doi":"10.1109/ASSCC.2016.7844207","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844207","url":null,"abstract":"This paper presents an ultra-broadband low-noise amplifier (LNA) operating from 16 to 43 GHz in a 0.25 pm SiGe:C BiCMOS technology. Across this band, the LNA achieves simultaneous low-noise performance (2.5–4.0 dB) and power matching (S11 < −10 dB) using dual-LC tank matching. The measured minimal noise figure is 2.5 dB at 26 GHz with an average value of 3.25 (±0.75) dB from 16 to 44 GHz. The best gain is 10.5 dB at 26 GHz with a 3-dB gain bandwidth from 16 to 43 GHz (90% fractional bandwidth). The measured input 1-dB compression point and input IP3 are better than −8.5 dBm and 1.8 dBm over the 16–43 GHz band, respectively, for a total power consumption of 24 mW.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132380989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844158
Mark Maddox, Baozhen Chen, M. Coln, Ron Kapusta, Junhua Shen, Lalinda D. Fernando
This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed unique ADC architecture and calibration technique addresses the issue of signal dependent reference voltage droop during SAR ADC bit trials and orthogonalize the bit weights to achieve 16bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the bit cap, the first reported in this type of SAR ADC. Measurement result from a prototype test chip shows +/−0.8 LSB (16-bit level) INL at 1MSPS.
{"title":"A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS","authors":"Mark Maddox, Baozhen Chen, M. Coln, Ron Kapusta, Junhua Shen, Lalinda D. Fernando","doi":"10.1109/ASSCC.2016.7844158","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844158","url":null,"abstract":"This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed unique ADC architecture and calibration technique addresses the issue of signal dependent reference voltage droop during SAR ADC bit trials and orthogonalize the bit weights to achieve 16bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the bit cap, the first reported in this type of SAR ADC. Measurement result from a prototype test chip shows +/−0.8 LSB (16-bit level) INL at 1MSPS.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1125 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120870307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844175
Jun Liu, Troy Bryant, N. Maghari, Jeffery Morroni
This paper presents a 90 nA quiescent current 1.5V–5.0V LDO regulator in a 0.35 um BiCMOS process. A new dual-loop (asynchronous digital loop and an analog loop) LDO is proposed. The digital loop (D-Loop) boosts the loop response speed under fast switching clock frequencies and the analog loop (Α-Loop) provides a clean output voltage with an ultra-low current consumption. The prototype IC achieves 90 nA of quiescent current during steady state with a power supply of up to 5.0 V. It has a drop-out voltage of 200 mV and a 50 mA output current capability. This prototype is implemented using a 0.35 um BiCMOS process and the active chip area is 0.25 mm2.
本文提出了一种基于0.35 um BiCMOS工艺的90 nA静态电流1.5V-5.0V LDO稳压器。提出了一种新的双环(异步数字环和模拟环)LDO。数字环路(D-Loop)在快速开关时钟频率下提高环路响应速度，模拟环路(Α-Loop)提供干净的输出电压和超低的电流消耗。在高达5.0 V的电源下，原型IC在稳定状态下实现了90na的静态电流。它具有200毫伏的降压和50毫安的输出电流能力。该原型采用0.35 um BiCMOS工艺实现，有源芯片面积为0.25 mm2。
{"title":"A 90nA quiescent current 1.5V–5V 50mA asynchronous folding LDO using dual loop control","authors":"Jun Liu, Troy Bryant, N. Maghari, Jeffery Morroni","doi":"10.1109/ASSCC.2016.7844175","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844175","url":null,"abstract":"This paper presents a 90 nA quiescent current 1.5V–5.0V LDO regulator in a 0.35 um BiCMOS process. A new dual-loop (asynchronous digital loop and an analog loop) LDO is proposed. The digital loop (D-Loop) boosts the loop response speed under fast switching clock frequencies and the analog loop (Α-Loop) provides a clean output voltage with an ultra-low current consumption. The prototype IC achieves 90 nA of quiescent current during steady state with a power supply of up to 5.0 V. It has a drop-out voltage of 200 mV and a 50 mA output current capability. This prototype is implemented using a 0.35 um BiCMOS process and the active chip area is 0.25 mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116007550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844185
Seongrim Choi, Jaemin Hwang, Suhwan Cho, Ara Kim, Byeong-Gyu Nam
A low-power and real-time hidden Markov model (HMM) accelerator is proposed for gesture user interfaces on wearable smart devices. HMM algorithm is widely used for sequence recognitions such as speech recognition and gesture recognition due to its best-in-class recognition accuracy. However, the HMM algorithm incorporates high computational complexity and requires massive memory bandwidth for sequence matches. There have been studies on hardware acceleration of the HMM algorithm to resolve these issues, but they were focused on the speech recognition and did not incorporate the motion orientation capability required for the gesture recognition case. In this paper, we propose an HMM accelerator incorporating the motion orientation block for gesture recognitions on wearable devices. Binary search is exploited in the motion orientation to avoid the division and arctangent associated with the orientation and reduce its arithmetic complexity. In addition, gesture models are clustered in the gesture database to save the memory bandwidth by reducing memory transactions. Moreover, logarithmic arithmetic is used in Viterbi decoding in the HMM for more reduction in its complexity. Thanks to these schemes, this work achieves 25.6% power reduction compared with a plain hardware implementation of the gesture recognizing HMM.
{"title":"A low-power real-time hidden Markov model accelerator for gesture user interface on wearable devices","authors":"Seongrim Choi, Jaemin Hwang, Suhwan Cho, Ara Kim, Byeong-Gyu Nam","doi":"10.1109/ASSCC.2016.7844185","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844185","url":null,"abstract":"A low-power and real-time hidden Markov model (HMM) accelerator is proposed for gesture user interfaces on wearable smart devices. HMM algorithm is widely used for sequence recognitions such as speech recognition and gesture recognition due to its best-in-class recognition accuracy. However, the HMM algorithm incorporates high computational complexity and requires massive memory bandwidth for sequence matches. There have been studies on hardware acceleration of the HMM algorithm to resolve these issues, but they were focused on the speech recognition and did not incorporate the motion orientation capability required for the gesture recognition case. In this paper, we propose an HMM accelerator incorporating the motion orientation block for gesture recognitions on wearable devices. Binary search is exploited in the motion orientation to avoid the division and arctangent associated with the orientation and reduce its arithmetic complexity. In addition, gesture models are clustered in the gesture database to save the memory bandwidth by reducing memory transactions. Moreover, logarithmic arithmetic is used in Viterbi decoding in the HMM for more reduction in its complexity. Thanks to these schemes, this work achieves 25.6% power reduction compared with a plain hardware implementation of the gesture recognizing HMM.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129602280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844164
Chuhong Duan, Andreas J. Gotterba, M. Sinangil, A. Chandrakasan
This paper presents a data-dependent SRAM paired with statistical methods to leverage data correlation for the purpose of low power read operations. A 10T bit-cell, a prediction-based conditional pre-charge circuit, and a compact column circuit implemented in a 16kbit 28nm SRAM test chip demonstrate power savings up to 69% for applications spanning signal processing, video coding and computer vision as compared to similar memories with naive prediction.
{"title":"Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics","authors":"Chuhong Duan, Andreas J. Gotterba, M. Sinangil, A. Chandrakasan","doi":"10.1109/ASSCC.2016.7844164","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844164","url":null,"abstract":"This paper presents a data-dependent SRAM paired with statistical methods to leverage data correlation for the purpose of low power read operations. A 10T bit-cell, a prediction-based conditional pre-charge circuit, and a compact column circuit implemented in a 16kbit 28nm SRAM test chip demonstrate power savings up to 69% for applications spanning signal processing, video coding and computer vision as compared to similar memories with naive prediction.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129611764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844206
Haikun Jia, C. Prawoto, B. Chi, Zhihua Wang, C. Yue
This paper presents a wideband millimeter-wave (mm-wave) power amplifier in 65nm CMOS. Coupled resonator based wideband matching technique is used in all the matching network. In the output matching network, the coupled resonator can achieve impedance transformation over a wide frequency range. In the input/inter-stage matching network, the uncoupled resonant frequencies of LC network at two sides of the coupled resonator are shifting towards opposite direction to extend the bandwidth and reduce ripple. The measured PA chip achieves 32.9% peak PAE, 15.3 dBm saturated output power. The fractional bandwidth is 63.3% from 21.6 to 41.6 GHz, which is the widest among reported bulk CMOS mm-wave PAs according to the authors' knowledge.
{"title":"A 32.9% PAE, 15.3 dBm, 21.6–41.6 GHz power amplifier in 65nm CMOS using coupled resonators","authors":"Haikun Jia, C. Prawoto, B. Chi, Zhihua Wang, C. Yue","doi":"10.1109/ASSCC.2016.7844206","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844206","url":null,"abstract":"This paper presents a wideband millimeter-wave (mm-wave) power amplifier in 65nm CMOS. Coupled resonator based wideband matching technique is used in all the matching network. In the output matching network, the coupled resonator can achieve impedance transformation over a wide frequency range. In the input/inter-stage matching network, the uncoupled resonant frequencies of LC network at two sides of the coupled resonator are shifting towards opposite direction to extend the bandwidth and reduce ripple. The measured PA chip achieves 32.9% peak PAE, 15.3 dBm saturated output power. The fractional bandwidth is 63.3% from 21.6 to 41.6 GHz, which is the widest among reported bulk CMOS mm-wave PAs according to the authors' knowledge.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116484196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844159
Kwuang-Han Chang, C. Hsieh
This paper presents a 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS with adaptive radix DAC, which achieves a synergistic integration of multi-bit-per-cycle and subradix techniques with adaptive error-tolerant redundancies. Alternative-reference-switching (ARS) DAC and adaptive-noise-reduction (ANR) comparator are developed to reduce the DAC effective switching capacitance by 47.4% and comparator power by 37.3%. The achieved peak SNDR, SFDR, and FoM are 61.7 dB, 74.4 dB and 10.3 fJ/conversion-step, respectively.
{"title":"A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS","authors":"Kwuang-Han Chang, C. Hsieh","doi":"10.1109/ASSCC.2016.7844159","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844159","url":null,"abstract":"This paper presents a 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS with adaptive radix DAC, which achieves a synergistic integration of multi-bit-per-cycle and subradix techniques with adaptive error-tolerant redundancies. Alternative-reference-switching (ARS) DAC and adaptive-noise-reduction (ANR) comparator are developed to reduce the DAC effective switching capacitance by 47.4% and comparator power by 37.3%. The achieved peak SNDR, SFDR, and FoM are 61.7 dB, 74.4 dB and 10.3 fJ/conversion-step, respectively.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114708217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844209
Xiaolong Liu, Chixiao Chen, Junyan Ren, H. Luong
This paper presents a transformer-based magnetic-tuning technique to achieve wide frequency tuning range and low power consumption for W-band oscillators without varactors. Fabricated in a 65-nm CMOS process, a dual-band VCO prototype measures frequency tuning range of 14.3% from 95.7 GHz to 110.5 GHz while consuming 6.2 mW, corresponding to a peak FOMt of −181.7 dBc/Hz at 10-MHz offset. In addition, a dual-band transformer coupling quadrature VCO (TC-QVCO) prototype achieves frequency tuning range of 12.1% from 89.4 GHz to 100.9 GHz while consuming 7.6 mW, corresponding to a peak FOMt of −178.8 dBc/Hz at 10-MHz offset. The measured quadrature phase error is less than 2.6° over the entire frequency range.
{"title":"Transformer-based varactor-less 96GHz–110GHz VCO and 89GHz–101GHz QVCO in 65nm CMOS","authors":"Xiaolong Liu, Chixiao Chen, Junyan Ren, H. Luong","doi":"10.1109/ASSCC.2016.7844209","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844209","url":null,"abstract":"This paper presents a transformer-based magnetic-tuning technique to achieve wide frequency tuning range and low power consumption for W-band oscillators without varactors. Fabricated in a 65-nm CMOS process, a dual-band VCO prototype measures frequency tuning range of 14.3% from 95.7 GHz to 110.5 GHz while consuming 6.2 mW, corresponding to a peak FOMt of −181.7 dBc/Hz at 10-MHz offset. In addition, a dual-band transformer coupling quadrature VCO (TC-QVCO) prototype achieves frequency tuning range of 12.1% from 89.4 GHz to 100.9 GHz while consuming 7.6 mW, corresponding to a peak FOMt of −178.8 dBc/Hz at 10-MHz offset. The measured quadrature phase error is less than 2.6° over the entire frequency range.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130787402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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