Fractional-N DPLL based low power clocking architecture for 1–14 Gb/s multi-standard transmitter

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-07-06 DOI:10.1109/JSSC.2017.2715160

Masum Hossain, W. El-Halwagy, A. D. Hossain, Aurangozeb

引用次数: 7

Abstract

This paper presents a low power clocking solution for multi-standard SerDes applications based on frac-N digital LC PLL for central clock generation and fractional-N ring PLL for local clock generation. The fractional-N LC PLL operates at 7–10 GHz consuming only 8 mW power and occupying 0.15 mm2 of silicon area with integrated jitter of 264 fs. Ring PLL covers from 800 MHz to 4 GHz to support the data rates between 1 to 14 Gb/s. The ring PLL supports dither-less fractional resolution of 250 MHz, corrects I/Q error with split tuning and achieves less than 400 fs integrated jitter. Transmitter works at 14 Gb/s with power efficiency of 0.80 pJ/bit.

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基于分数n DPLL的1 - 14gb /s多标准发射机低功耗时钟架构

本文提出了一种适用于多标准SerDes应用的低功耗时钟解决方案，该方案采用分数n数字LC锁相环作为中心时钟生成，分数n环锁相环作为本地时钟生成。分数n LC锁相环工作在7-10 GHz，功耗仅为8 mW，硅面积为0.15 mm2，集成抖动为264 fs。环锁相环覆盖范围从800 MHz到4 GHz，支持1到14 Gb/s的数据速率。环形锁相环支持250 MHz的无抖动分数分辨率，通过分割调谐校正I/Q误差并实现小于400 fs的集成抖动。发射机工作速率为14gb /s，功率效率为0.80 pJ/bit。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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Copyright page Fractional-N DPLL based low power clocking architecture for 1–14 Gb/s multi-standard transmitter A 16–43 GHz low-noise amplifer with 2.5–4.0 dB noise figure A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS A low-power calibration-free fractional-N digital PLL with high linear phase interpolator