Performance-driven interconnection optimization for microarchitecture synthesis

Abstract

The interconnection synthesis problem in microarchitecture-level designs is addressed. With emphasis on the speed of data movement operations, algorithms are proposed that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. Two types of problems are considered: resource-constrained binding and performance-constrained binding. The integer linear programming (ILP) formulations are derived to optimally solve these problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Experimental results indicate that the proposed algorithms are very effective.<>