K. Okumura, S. Ohya, M. Yamamoto, T. Watanabe, Y. Shimamura, M. Kikuchi
{"title":"A 1Mb EPROM","authors":"K. Okumura, S. Ohya, M. Yamamoto, T. Watanabe, Y. Shimamura, M. Kikuchi","doi":"10.1109/ISSCC.1984.1156663","DOIUrl":null,"url":null,"abstract":"A 1Mb fully static EPROM utilizing a 1.2μm design rule technology will be discussed. The chip features typical access time of 200ns, a programming voltage of approximately 13V, and can be used either as 64K × 16 or 128K × 8 organization.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A 1Mb fully static EPROM utilizing a 1.2μm design rule technology will be discussed. The chip features typical access time of 200ns, a programming voltage of approximately 13V, and can be used either as 64K × 16 or 128K × 8 organization.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
