Novel Adders for Xilinx Versal FPGAs

Abstract

Compact addition circuits for new Xilinx Versal FPGA devices are presented in this paper. A new column compression technique that achieves complete logic utilization of Versal LUT6 is discussed. This technique enables area reduction for multi-operand adders. The LUT count for multi-operand addition is reduced by up to 50% compared to previous generation FPGAs. Compact binary adders, which are smaller by 25%, are also discussed. The proposed binary adders have lower performance compared to standard method due to not using dedicated carry chain.