A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2016-11-01 DOI:10.1109/ASSCC.2016.7844184

Sungpill Choi, Seongwook Park, H. Yoo

引用次数: 0

Abstract

A low-power depth-estimation processor is proposed for mobile UI applications. We adopt hardware-friendly shift-only computations for exponentiation and multiplication in stereo algorithm to reduce power consumption down to 4.7mW with negligible accuracy loss. Also, the 7-stage shifter-register-based pipeline architecture with applying pipeline reordering optimization is deployed for reducing power and area. Utilization of the proposed pipeline architecture is 94% at 166MHz. The proposed algorithm and hardware co-optimization reduces required number of operations and external memory accesses by 85.5%, resulting in 75.6% lower energy consumption. The 1.47mm2 chip is fabricated with 65nm CMOS process and the resulting depth map is successfully used for hand segmentation.

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一种34pJ/level像素深度估计处理器，基于移位器的流水线架构，用于移动用户界面

提出了一种用于移动UI应用的低功耗深度估计处理器。我们在立体算法中采用硬件友好的移位计算来进行幂和乘法运算，将功耗降低到4.7mW，精度损失可以忽略不计。此外，采用了基于移位寄存器的7级管道架构，并应用管道重新排序优化，以降低功耗和面积。在166MHz时，所提出的管道架构的利用率为94%。该算法和硬件协同优化将所需的操作次数和外部存储器访问减少了85.5%，从而降低了75.6%的能耗。采用65nm CMOS工艺制作了1.47mm2的芯片，并成功地将得到的深度图用于手分割。

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2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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