Wire-Speed Multirate Accelerator for Aggregation Operations on Sorted Data

S. Jun, A. Arvind
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Abstract

We present an accelerator architecture for wire-speed aggregation of sorted key-value pairs on a wide datapath, in a bump-in-the-wire fashion. The presented accelerator is capable of maintaining wire-speed regardless of data distribution, even when (1) the aggregation function has multiple-cycle latency, and (2) the input stream is multi-rate, i.e., multiple elements arrive every cycle. To the best of our knowledge, it is the first accelerator architecture that satisfies both properties.
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用于排序数据聚合操作的线速多速率加速器
我们提出了一种加速器架构,用于在宽数据路径上以线中碰撞方式对排序键值对进行线速聚合。无论数据分布如何,所提出的加速器都能够保持线速,即使(1)聚合函数具有多周期延迟,(2)输入流是多速率的,即每个周期都有多个元素到达。据我们所知,它是第一个同时满足这两个属性的加速器架构。
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